So, hello to all viewers and welcome back to Gettobyte Platform. In This blog you are going to know about RFID Reader MFRC522, which is designed by NXP Semiconductors. Objective would be to interface this module with Host MCU’s like of NXP Semiconductors, STMicroelectronics or other vendors MCU’s. Will make the driver to interface the RFID Reader with any MCU, not unlike just with Arduino and Arduino IDE environment. To make the driver of RFID reader at first, we need to dig into its datasheet, to understand its various sub parts. And that’s all about this blog is gotten going to be, to make the datasheet understand in easy way-out.
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RFID Technology
RFID modules is a wireless sensing technology which is used to track/identify/monitor the objects.
MFRC522 RFID Reader/PCD
MFRC522 is a highly integrated reader/writer IC for contactless communication at 13.56 MHz. These reader supports the ISO 14443 A protocol for communicating with RFID Tags. They are used to detect the MIFRAME RFID tags.
MFRC522 has internal RF transceiver, which provides a robust and efficient implementation for demodulating and decoding signals from MIFRAME compatible cards using ISO 14443 A protocol. The digital module of MFRC522 manages the complete ISO/IEC 14443 A framing and error detection (parity and CRC) functionality.
MFRC522 supports 3 tags of MIFRAME family, that are MF1xxS20, MF1xxS70 and MF1S50 products.
MFRC522 features
MFRC522 though quite old RFID reader and in today’s time many new advance RFID readers have come up. But so as to get started with this technology as a hobbyist/student/DIY project, it is perfect module to lay your hands on this Technology.
- MFRC522 has highly integrated analog circuitry to demodulate and decode responses when RFID tags are brought in close proximity of these devices.
- RFID readers are connected with some host MCU, where the processing of data which is received via RFID tags happens according to the application. MFRC522 can connect with host MCU, using SPI, Serial UART and I2C -bus interface.
- It supports ISO 14443 A protocol and can be used with MIFRAME family of RFID tags. And in MIFRAME family it supports only MF1xxS20, MF1xxS70 and MF1xxS50 products.
- It has internal CRC-coprocessor.
- Internal FIFO buffer which can handle 64 bytes of sending and receiving.
- It uses the Crypto-1 cipher for authenticating.
- It supports Internal oscillator for connection to 27.12 MHz quartz crytsal.
- It is low power device, need 2.5 V to 3.3 V power supply.
- It also has flexible interrupt modes when some RFID tags are detected and trigering events too. In addition to flexible interrupt, it has programmabe I/O pins and timer.
- It can perform Internal self-test too.
MFRC522 Functional description
MFRC522 Host Interfaces
MFRC522 can be connected to Host MCU using 3 serial protocols: UART, I2C or SPI.
MFRC522 checks the current host interface type.
automatically after performing a power-on or hard reset. The MFRC522 IC identifies the host
interface by sensing the logic levels on the below pins after the reset phase. 
The MFRC522 is equipped with a series of registers that allow the Host MCU to access its functional description blocks. To ensure the proper functioning of the MFRC522, the Host MCU must initialize and configure these functional blocks by sending the corresponding register addresses.
Each register is essentially an address byte that is transmitted from the Host MCU. Depending on the function described in the register section, read/write operations are performed on the corresponding address byte.
It is crucial to properly initialize and configure these functional blocks to ensure the optimal performance of the MFRC522. By understanding the purpose of each register and its corresponding function, the Host MCU can effectively communicate with the MFRC522 and achieve the desired results.
–> MFRC522_write_register()
–> MFRC522_Read_register()
MFRC522 Interrupts
MFRC522 can trigger the interrupts, when certain events occur. There are 8 events as shown in below table when interrupt can be triggered.
When above event occurs, IRQ pin is used to interrupt the host. IRQ pin signal is asserted and host MCU can use its interrupt handling capabilities (basically NVIC if we are talking about ARM based MCU) on what to do when corresponding interrupt has occurred.
- Status1Reg Register IRq bit is used to indicate if any interrupt source has been triggerered.
- Which interrupt has been triggered is indicated by ComIrqReg and DivIrqReg Register. 
- Which interrupts to be configured and behavior of IRQ pin is configured by ComIEReg and DivIEReg Register.
MFRC522 Time Unit
There is a Timer unit in MFRC522, that is used for multiple purposes. Timer unit is essential for maintaing the configuring the clock and analog interfaces. Also timer unit can be used for following features:
- Timeout counter
- Watchdog counter
- Stopwatch
- Programmable one shot
- Periodical trigger
Timer has an input clock of 13.56 MHz derived from the 27.12 MHz quartz crystal oscillator. The timer consists of 2 stages: prescaler and counter.
- The prescaler(TPrescaler) is a 12-bit counter. That can be configured using TModeReg register’s TPrescaler_Hi[3:0] and TPrescalerReg register’s TPrescaler[7:0] bits.
- The Reload value for the counter is defined by 16 bits between 0 & 65535 in the TReloadReg register.
- The current value of the timer is indicated in the TCounterVAlReg Register.
MFRC522 FIFO
FIFO overview
The MFRC522 contains an internal FIFO buffer of 64 bytes, which is equivalent to 8 x 64 bits. This buffer is utilized for both input and output data streams. The host MCU has the capability to perform both Read and Write operations on this FIFO. The host MCU sends commands to PCD for communication with PICC. these commands are specified in ISO14443 A standard, which is then inputted into the FIFO. When the PICC responds to these commands, the response is also stored in the FIFO. The host MCU can then read the FIFO to obtain the response from the PICC.
The FIFO buffer is a crucial component in the communication process between the host MCU and the PICC. It allows for efficient data transfer and ensures that all responses are stored in a centralized location. The ability to perform both Read and Write operations on the FIFO provides flexibility and control to the host MCU. By utilizing the FIFO buffer, the communication process is streamlined and optimized for maximum efficiency.
About FIFO registers
FIFO buffer input and output data bus is connected to the FIFODataReg register. Writing to this register stores one byte in the FIFO buffer and increments the internal FIFO buffer write pointer. Reading from this register shows the FIFO buffer contents stored in FIFO read pointer and decrements the FIFO buffer read pointer.
Only one FIFO buffer has been implemented which can be used for input and output. The microcontroller must
ensure that there is not any unintentional FIFO buffer accesses.
The FIFOLevelReg is utilized to determine the number of bytes stored in the FIFO. This register is particularly useful in checking the number of bytes received in the FIFO buffer when the PICC sends a response to the PCD command. By using the FIFOLevelReg, you can easily keep track of the amount of data stored in the FIFO, which is essential in ensuring the smooth operation of your system.
One can also get the status of FIFO buffer using status and error registers.
- FIFO buffer almost full warning can be got to know from Status1Reg register’s HiAlert bit.
- FIFO buffer almost empty warning can be got to know from Status1Reg register’s LoAlert bit.
- FIFO buffer overflow warning, using ErrorReg register’s BufferOvfl bit.
MFRC522 CRC
MFRC522 has a Cyclic Rebudency Check (CRC) coprocessor to check the integrity of the data when data from PICC is received or when data is wriiten to PICC.
- CRC has preset value 0000h, 6363h, A671h or FFFFh. We can configure the preset values using ModeReg CRCPreset[1:0].
- CRC polynomial for the 16-bit CRC is fixed to x^16 + x^12 + x^5 + 1.
- CRCResultReg register indicates the result of the CRC calculation.
- CRC algorithm which is used is according to ISO/IEC 14443 A and ITU-T.
To perform the CRC calculation refer its state machine in below section.
MFRC522 Command Set
MFRC522 operation is determined by certain commands. According to these commands, correspondingly MFRC522 would be performing some action.
So, it’s like at first, we will configure the FIFO, CRC, Interrupts and timer unit. After that Host MCU will instruct the commands to MFRC522 in order to tell what it has to do. Host MCU will write the command code to the CommandReg Register.
Main commands that would be used are Idle, Transceive, CalcCRC and Transmit commands. Transceive command is the one which has to be sent from Host MCU to MFRC522 to send the FIFO buffer data to the antenna, which is further propagated to the RFID readers. And according to the data which we have written in FIFO RFID readers would act and give response.
Each command that needs a data bit stream (or data byte stream) as an input immediately processes any data in the FIFO buffer. An exception to this rule is the
Transceive command. Using this command, transmission is started with the BitFramingReg register’s StartSend bit.
MFRC522 Block Diagram
Above is the simplified block diagram of MFRC522 module. MFRC522 has an internal memory, power supply, interrupt pins, FIFO buffer, Antenna and analog interface, digital module for communicating with Host MCU.
Analog Interface handles the modulation and demodulation of the analog signals. FIFO Buffer ensures fast and convenient data transfer.
Register bank are the set of registers through which MFRC522 would be configured and initialized to use. Parameters like Clock, Interrupts, status of errors while communicating with RFID readers, CRC calculation, FIFO configuration and etc need to be configured before using the MFRC522.
How the MFRC522 Internal system works?
Host MCU will send PCD Commands to MFRC522, according to which it will perform some operations. MCU will send these commands by writing into one of the registers of PCD.( For MFRC522 CommandReg is register)
Operations like:
- Activation of CRC Coprocessor
- Transmission of data from FIFO buffer of MFRC522 and activation of receiver circuits to get the response from PICC
- transfer of data from FIFO to an internal buffer
- soft reset and authentication-based operations
Further MFRC522 will emit the commands for communicating with PICC, here referred to as PICC Commands, according to which operation with PICC takes place, like scanning of PICC, selecting the PICC, reading and writing the data on PICC. MFRC522 emits these commands via electromagnetic induction and electric coupling. ( That is the main working principle behind the RFID technology)
Host MCU to PCD
Host MCU will send the commands to PCD, according to which PCD will perform the operations like activation of FIFO buffer or CRC coprocessor, and transmission of data from FIFO. We will name these commands as MFRC522 Commands sets. Host MCU will send those commands to PCD (here MFRC522) by writing into the CommandReg Register using low level Host Interface write API.
- Idle Command: Places the MFRC522 in Idle mode.
- Mem Command: Transfers the 25 bytes from the FIFO Buffer to the internal buffer. This command is used when, we want to read the data from PICC( As described in ISO-14443-4 doc), as PICC response is always recorded in PCD FIFO.
- Generate RandomID: generates a 10-byte random ID number.
- CalcCRC: Activates the CRC coprocessor or performs a self test.
- Transmit: transmit data from the FIFO buffer
- NoCmdChange: no command change, can be used to modify the CommandRef register bits without affecting the command
- Receive: activates the receiver circuits
- Transceive: Transmit data from the FIFO buffer to antenna and automatically activates the receiver after transmission.
- MFAuthent: performs the MIFARE standard authentication as a reader
- SoftReset: This command performs a reset of the device. The configuration data of the internal buffer remains unchanged. All registers are set to the reset values. This command automatically terminates when finished.
PCD to PICC
Further there are also command set which PCD have to emit to communicate with PICC and enter the PICC into some state machine.
PICC States:
- Power-off State: In the POWER-OFF state, the PICC is not powered by a PCD operating field
- Idle State: In the IDLE state, the PICC is powered. It listens for commands and shall recognize REQA and WUPA commands.
- Ready State: Cascade levels are handled inside this state to get the complete UID. PICC enters the ACTIVE state when it is selected with its complete UID.
- Active State: PICC complies with ISO-14443-4 to accept protocol activation commands (RATS)
- HALT State: In this state PICC only responds to WUPA command.
- Protocol State: PICC behaves according to 1s014443-4 specifications.
We will name these commands as PICC commands. Host MCU will write these PICC command into the PCD FIFO (refer the MFRC522 FIFO section on how to write the data on FIFO). PCD would transmit the FIFO data when it enters the Transceiver state machine (refer above topic).
PCD would transmit these commands via the electromagnetic induction and communicates with PICC via electronic coupling. PCD’s have RF transceivers through which it emits the electromagnetic waves with commands sets encoded in them. PICC have antenna and small circuitry, which gets energized via electromagnetic waves emitted by PCD and then further both PCD and PICC get coupled together to have 2 way wireless communication. How PCD would send commands to PICC and in return how PICC would respond, that is done according to IS014443 protocol. ISO14443 specifies all the frame formats,PICC command and their format , modulation schemes for RFID technology. 
PICC Frame formats:
- Short Frame:
- Standard Frames
PICC Command Set:
- REQA/WUPA Command: This command is send by PCD to scan the valid and IS014443 compatible PICC’s. This command is in short frame format. Host MCU will write this command into the PCD FIFO, from where this command is transmitted and emitted wirelessly. Response to this command is with ATQA. PICC are in Idle state when listening to this command and after successfully transmitting the ATQA response they enter into Ready State. These commands consist of 7 bits, as specified below:
- ANTICOLLISION/SELECT Command: PICC are in ready state when listening to this command and after this command they enter into ACTIVE STATE. This Command is used to get the UID of the scanned PICC and further select the corresponding PICC for Reading and writing data from it. For the MF1S503 PICC’s UID is of 4 bytes, for that only 1 cascade level is needed.
These commands need to be configured and then these bytes are written into The PCD FIFO for transmission and emission of signal to PICC wirelessly. This Command consists of:
- Select code SEL(1byte): Specify the cascade level.
- No of valid bits NVB (1 byte): specify number of bytes that would be transmitted by PCD to PICC (including SEL, NVB and below point)
- 0 to 40 data bits of UID according to value of NVB.
ANTICOLLISION Command consist of:
- Select Code: Cascade level 1= 0x93
- No of valid bits NVB = 0x20
Response to ANTICOLLISION Command is with the UID of the Scanned PICC(0xEA, 0x24, 0x77, 0x15) and its CRC(0xAC).
- SELECT Command consists of:
- Select code: Cascade level 1 = 0x93
- No of valid bits NVB – 0x70
- 0 to 40 data bits of UID that has been received in ANTICOLLISION Command( 0xEA, 0x24, 0x77, 0x15)
- CRCA(1 byte) : CRC of SELECT Command would be calculated by PCD and then it would be sent to PICC. And When PICC receives the SELECT Command it will check this CRCA and then will send the ACK.(0xAC)
Response to SELECT Command is with the Select Acknowledge:
MFRC522 Hardware and Pinout
MFRC522 IC has 32 pins in total and it comes in SOT617-1 package.
Pin description can be found from the datasheet of MFRC522. To use the MFRC522 IC its module is widely available and quite inexpensive. Can be brought from Robu at cost of 150 rupees. With the module an RFID tag and a key fob tag of MIFRAME Classic 1KB comes in.
In MFRC522 module, IC has 8 pins exposed out for connection and connecting to host MCU.
- The module has 4 pins exposed out for connecting it to host MCU using either SPI, I2C or UART. By default, reader can communicate with a microcontroller over a 4-pin SPI with a maximum data rate of 10 Mbps. It also supports I2C and UART protocols. As told in MFRC522 functional description part, MFRC522 checks the host interface type automatically depending on the signals on it’s control pins.
- MFRC522 module has 1 interrupt pin also exposed out, which can be used to trigger interrupts to alert the microcontroller when a RFID tag is in the vicinity.
- And remaining 3 pins are power supply pins and a reset pin. Reset pin is used for power down mode and reset signal. Module requires the power supply of 3.3 V, that is provided via VCC and GND pins.
Other vendor RFID readers
STMicroelectronics
Texas Instruments
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W25Q128JV SPI Flash Memory: Part3
Table of Contents So continuing with the blog series of, W25Q128 SPI based flash memory\’s , in the previous blogs W25Q128JV SPI Flash Memory: Part1 | gettobyte W25Q128JV SPI Flash Memory: Part2 | gettobyte we have gone through the introduction and overview for W25Q128JV flash memory\’s. From this blog we are going to start with the Application and Device driver development of W25Q128JV IC. The Driver which i am going to develop in this blog will be generic can be used with any MCU, by just replacing the SPI API\’s. This application driver will be generic and simple one which will be having API\’s to perform basic Operation on this chip. We will be creating the 2 files, header file and source file(.h &.c) for W25Q128JV Application driver. Header file(.h) will be having all the Macros, Typedefs, Enums, Structures and function declarations. Source file(.c) will be having all the function definitions and local variables to be used in the driver. Header file (W25Q128JV.h) First thing that we are going to do is define the Object like Macro\’s for all the registers of W25Q128JV in the header file(.h) of W25Q128JV. Macros are widely used in Embedded Programming for referring the registers address with the acronym of the Register names, so that it is easy for developer/user to understand the code or using the API. Like, above if we want to read the JEDECID of the chip, instead of writing 0x9F in the Application code we can pass the Macro JEDECID. (Though we are not going to use all the registers of W25Q128, as in this blog we are just going to make the driver for following features. The Application driver will be having API\’s for reading-writing the data, erasing the data, reading-writing of Status registers, reading JEDEC ID , chip erase and chip initialise.) /* * w25q128jv.h * * Created on: 15-Apr-2021 * Author: kunal */ #define WriteEnable 0x06 #define WriteDisable 0x04 #define Dummybyte 0xA5 #define ReadSR1 0x05 #define WriteSR1 0x01 #define ReadSR2 0x35 //0x35: 00110101 #define WriteSR2 0x31 #define ReadSR3 0x15 #define WriteSR3 0x11 #define Write_Enab_for_Vol_status_regist 0x50 #define ReadData 0x03 #define WriteData 0x02 #define ReadDataFast 0x0B #define JEDECID 0x9F #define UinqueID 0x4B #define SectErase4KB 0x20 #define SectErase32KB 0x52 #define SectErase64KB 0xD8 #define chiperase 0xC7 #define reset1 0x66 #define reset2 0x99 #define read_addr1 0x020000 #define read_addr2 0x030000 #define read_addr3 0x040000 #define BUSY_BIT 0x01 #define WRITE_ENABLE_LATCH 0x02 Next thing in Header file will be the function definitions that would be used for interacting with the W25Q128JV flash memory\’s. void W25_Reset (void); void WriteEnable_flash(); void W25_Read_Data(uint32_t addr, char block[], uint32_t sz); void W25_Write_Data(uint32_t addr, char block[], uint32_t sz); uint32_t W25_Read_ID(void); void W25_Ini(void); void erase_sector4KB(uint32_t addr); void erase_sector32KB(uint32_t addr); void erase_sector64KB(uint32_t addr); void chip_erase(); void Uinque_ID(uint8_t uinque[]); void WriteSR(uint8_t SR_address, uint8_t SR_data); uint8_t ReadSR(uint8_t SR_address); void WaitForWriteEnd(void); Apart from Object like Macro\’s and Function definition\’s their would be 2 additional function like Macro\’s. //For STM32 CUBEMX #define cs_set() HAL_GPIO_WritePin(GPIOA,GPIO_PIN_4,GPIO_PIN_SET) #define cs_reset() HAL_GPIO_WritePin(GPIOA,GPIO_PIN_4,GPIO_PIN_RESET) //For STM32 BareMetal #define cs_set() GPIOA->ODR |= GPIO_ODR_ODR4; #define cs_reset() GPIOA->ODR &= ~GPIO_ODR_ODR4; As we are going to interface the W25Q128JV via SPI peripheral to our MCU\’s, in which MCU would be the Master device and W25Q128JV would be slave device. And in SPI -> Chip Select/Chip Enable pin is used for selecting the slave. Thus these 2 Macro\’s would be used for selecting the slave before the SPI instructions are send ( by using the cs_set()) and then deselecting the slave after the SPI instructions( by using the cs_reset()). Source file(W25q128JV.c) This file would be having all the function declarations of the functions which are defined in (W25Q128JV.h). The 2 most important API\’s which will Send and Receive the SPI commands are: void SPI1_Send (uint8_t *dt, uint16_t cnt) { HAL_SPI_Transmit (&hspi1, dt, cnt, 5000); } void SPI1_Recv (uint8_t *dt, uint16_t cnt) { HAL_SPI_Receive (&hspi1, dt, cnt, 5000); } API\’s Explained for Device Driver of W25Q128JV: void SPI1_Send () This function is wrapper for transmitting the data via SPI. not be used directly in Application driver, but it will always be called by Other API\’s of the driver to send the command to W25Q via SPI. It has 2 parameters: 1) uint8_t *dt –>pointer to store the data that will be transmitted from the Host MCU to W25Q128JV. 2) uint16_t cnt –> Variable that will be storing the size of data that has to be transmitted from MCU to W25Q128JV. void SPI1_Send (uint8_t *dt, uint16_t cnt) { HAL_SPI_Transmit (&hspi1, dt, cnt, 5000); } void SPI1_Recv() This function is wrapper for receiving the data via SPI. This API is also not used directly by the Application Driver, but will be used by the other API\’s of the driver for receivng the data from W25Q via SPI. It also has 2 parameters: uint8_t *dt –> pointer to store the data that will be received from the W25Q128JV. uint16_t cnt –> variable that will be storing the size of data that has to be received. void SPI1_Recv (uint8_t *dt, uint16_t cnt) { HAL_SPI_Receive (&hspi1, dt, cnt, 5000); } void W25_Reset(): W25Q SPI flash Ic\’s come in small package and they have limited number of the pins. Thus W25Q provides the software reset instruction feature. User/Developer can reset the W25Q by sending the specified instructions to W25Q via SPI. After reset the device will come to its default state and loose all volatile content. Enable reset – 0x66( reset 1 macro) and Reset – 0x99( reset 2 macro)are the instructions that has to be send for generating the software reset. These 2 instructions has to be send in sequence, as any other command after the Enable reset command( 0x66) apart from Reset(0x99) will disable the reset procedure. Once the reset command is accepted it woulfd take approx 30us to reset the W25Q IC. void W25_Reset (void) { cs_reset(); tx_buf[0] = reset1; tx_buf[1] = reset2; SPI1_Send(tx_buf, 2); cs_set(); } void WriteEnable_flash(): In W25Q, before writing to any Page, Erasing any sector/block or performing full chip erase. We have to send the Write enable Instruction via SPI.
FreeMaster Debugging Tool
Add Your Heading Text Here Lorem ipsum dolor sit amet, consectetur adipiscing elit. Ut elit tellus, luctus nec ullamcorper mattis, pulvinar dapibus leo. Author: Kunal Gupta
W25Q128JV SPI Flash Memory: Part2
Table of Contents So guys this is the continued blog on my interfacing W25Q128JV SPI flash memory with STM32 and AVR MCU. So in the last blog we have started with W25Q128 overview, its features and pin descriptions. Now in this blog we are going to talk about following topic: SPI standard instructions. Status and Configuration Registers of W25Q128JV SPI Serial Flash memory. Write protection features. About its block diagram of memory mapping & management. and then going to understand Status and Configuration Registers. Then in next blog we are going to start with its driver implementation on STM32 and AVR MCU. SPI Standard Instructions So as I have mentioned that module which we are going to use has standard SPI pins only on the breakout module( one can buy this module from robu). Remember the pinout of W25Q128 from last blog??? If not kindly refer to that W25Q128JV SPI Flash Memory: Part1 once before going further in this topic. W25Q128JV IO2 and IO1 pins are not available in the modules which we are going to use and buy. We can operate the SPI at mode 0(0,0) or mode 3(1,1), that is SPI CPHA or CPOL bits would be either 0,0 or 1,1. W25Q128JV would be used as a slave and host MCU would be used as a master. In standard SPI we can run this IC at frequency of 133MHZ for read-write operations. But in our sample codes i would be using the IC at 1 MHZ. Most Significant bit(MSB) is sent first during the SPI communication. Chip select pin(CS) would be used for selecting the slave. When CS is set as low, the slave is selected and when CS is set as HIGH, the slave would not be selected. Serial Data Input( DI) is the MOSI pin and Serial Data Output(DO) is the MISO pin. Serial Clock Input (CLK) pin is used as Serial Clock for SPI communication. During configuring of SPI pins for our host MCU, CS pin of the host MCU would be configured as Output pin. MOSI pin of the host MCU would be configured as OUTPUT pin. SCLK pin of the host MCU would be configured as INPUT pin. MISO pin of the host MCU would be configured as INPUT pin. Dual and Quad SPI are not of our concern, so we are not going to dig deep into those in this blog. though we are going to discuss standard SPI only if anybody has any things to ask related to Dual and Quad SPI they can reach out to me via gettobyte community. Status and Configuration Registers These are very important registers, plays an important role in configuring and using these memory chips. Their are 3 Status registers, SR1,SR2,SR3. Status register provide the status on the availability of the flash memory array, whether the device is write enabled or disabled, the state of the write protection, QUAD SPI settings, Security register lock status, and Erase/Program suspend status, output driver strength, and power up status. Also, status registers are used to configure the device write protection failures, QUAD SPI settings, Security register OTP locks and output driver strength. Each Status register can be read and write by specific commands. For reading the status register we have to issue the Read status register instructions for reading the corresponding Status register. One can read the Status registers of the memory chip when we want to know the status on the availability of the flash memory array, whether the device is write enabled or disabled, the state of the write protection, QUAD SPI settings, Security register lock status, Erase/Program suspend status, output driver strength, and power up status. For writing the status register we have to issue the write status register instructions for the corresponding Status register. One can write on the status registers when we want to configure the chip for the device write protection failures, QUAD SPI settings, Security register OTP locks and output driver strength. Status Register 1 S0: BUSY bit –> BUSY is a read-only bit in the status register (S0) that is set to a 1 state when the device is executing a Page Program(02h), Quad Page Program(32h), Sector Erase(20h), Block Erase(52h), Chip Erase(60h), Write Status Register(01h,31h,11h) or Erase/Program Security Register instruction(44h/42h). During this time the device will ignore further instructions except for the Read Status Register. So in short we can use this bit inside the while loop or if loop to check whether the device is ready for further instructions or not. erase_sector4KB(read_addr1); // device is executing a erase sector instruction if((ReadSR(ReadSR1) & BUSY_BIT) == 0x01) // Busy bit is set when erase sector instruction is send, so checking that { erase_sector4KB(read_addr1); } S1:WEL –> Write enable latch is also a read-only bit that is set to 1 after executing a Write enable instruction and making the chip in write enabled mode. Prior to every Page Program(02h), Quad Page Program(32h), Sector Erase(20h), Block Erase(52h), Chip Erase(60h), Write Status Register(01h,31h,11h) or Erase/Program Security Register instruction(44h/42h) we have to send the Write enable instruction. So after sending the write enable instruction we can read this bit to check whether Write enable Instruction is executed or not. It is cleared to 0 when the device is written disabled. Write disabled state occurs after the Page Program(02h), Quad Page Program(32h), Sector Erase(20h), Block Erase(52h), Chip Erase(60h), Write Status Register(01h,31h,11h) or Erase/Program Security Register instruction(44h/42h). So in short we can say that the WEL bit is used to check whether Write enable Instruction is executed or not. S2-S3-S4: Block Protect Bits(BP2, BP1, BP0) –> are read/write bits that can be used to protect the memory array from Program or erase instructions. One can protect ALL, NONE, or PORTION of the memory, corresponding configurations can be done for BP2, BP1, and BP0 bits according to the below tables. Also, see the TB and SEC bits for Write protection configurations S5: Top/Bottom BLOCK Protect(TB)–> This bit controls whether the memory protection has to be performed from TOP
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In the new age of autonomous and connected vehicles, cyber-attacks in automotive are happening frequently. Discover in this blog, what technology is used to make our vehicles safe and secure.
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