Table of Contents W25Q128JV SPI Flash Memory interfacing with STM32 and AVR MCU So hello guys, welcome back to the Gettobyte once again. As I have told you that we are going to start with application codes also, so now in this blog what we are going to do?? We are going to interface the W25Q128JV SPI Serial flash memory module to our STM32 MCU and AVR8 MCU. Now let’s look at how this module looks. This module is very small and packed into small sizes. One can buy it easily from the Amazon Website. This module has 6 pins: VCC, GND, and 4 SPI Communication pins( MOSI, MISO, CE & SCK). But the IC has much more pins, that I will be briefing below. W25Q128JV SPI Flash Memory module Now starting with this Flash memory, In this blog, I will be telling you about its: General description of the IC. Features of this Serial Flash Memory. Pin Description. In the next subsequent blogs will be making the application code on AVR and STM32 MCU using SPI peripheral and peripheral driver. At first, will be making the application code on AVR MCU and then on STM32 MCU. So now moving forward, let’s begin our journey to it. General Description of W25Q SPI flash memory So starting with W25Q128JV. These are the Serial communication-based Flash memories into which we can store data. These can work as RAM memory for memory constraint embedded MCUs. We can transfer data from these memory chips in standard SPI serial communication up to a frequency of 133 MHZ and when used in Dual/Quad SPI Serial communication, data transfer frequency can go up to 236MHZ/532 MHZ. So one can read, write and fetch data from these memory chips at very high frequencies. These have 65536 programmable page lengths and in total there are 256 pages. That means it has 256 pages and on each page, we can write 65536 bytes.  W25Q SPI flash memory depicted as a book On each byte of these pages, we can read and write at a redundancy of 10000 times. Up to 256 bytes can be programmed at a time. We will go into more detail when we will understand its block diagram of memory mapping and management. Features of W25Q SPI Flash Memory It can run on Standard SPI, DUAL SPI, and QUAD SPI. Standard SPI: is traditional SPI Protocol which has CLK,CS,MISO(DO),MOSI(DI) pins.  In this, we have 1 pin(MOSI) for sending data from Master to Slave and another pin (MISO) for sending data from slave to master. It can run at Max speed of 133MHZ for standard SPI. To know more about SPI, refer to this blog  Dual SPI: In DUAL SPI, we have 2 Output/Input pins. Which means at a time we can send data from 2 pins and receive data from 2 pins. Refer the below image, DI becomes IO0 and D0 becomes IO1, so at a time we can send and receive data from both of those pins. As 1 byte has 8 bits and bits 0 and 1 of my one byte are being transmitted or received simultaneously, thus our data transfer becomes 2x then standard SPI, where only 1 bit is commuted at a time. In Dual SPI Max speed it can run at is 266 MHZ.  DUAL SPI QUAD SPI: In QUAD SPI, we have 4 Output/Input pins. Which means at a time we can send data from 4 pins and receive data from 4 pins. IO0,IO1,IO2,IO3 are the 4 pins from which data is commuted between slave and master. In Quad SPI MAX speed it can run at is 532 MHZ.  QUAD SPI One can perform 100k program-erase cycles per sector and it has data retention for more than 20 years. Efficient continuously read for about 8/16/32 byte warp. Byte warp here means that it can read memory continuously in the chunks of 8/16/32 bytes in one single time. Lets say it is reading in 8 byte wrap, so at first read it will read 0-7 bytes, then in next 8-15 bytes, then 16-23 bytes. Then the other important thing is Advance Security features which this IC has. You will be able to understand these features in better way when we will go through the Status and Configuration registers of this IC. On the memory chip, We can lock the certain memory bytes, that is no one can write or read on configured memory bytes or size. We can use the OTP (one time password) to have password based memory protection We can access the memory bytes of the IC, in Blocks(64 KB), sectors(4KB) or single byte. Starting from the Top of memory or from the Bottom of memory. PINOUT of the W25Q128 Flash memory chip So W25Q128 has 8 pins. Depending on the package we have, the number of pins of the IC can increase or decrease. The module which we will be using is packaging WSON.Pin number 1 is CE (Chip Select), used to select the SPI slave by making a LOW signal to this pinPin number 2 is DO (Data Output), that is MISO pin in case of standard SPI and IO1 in case of DUAL/QUAD SPI.Pin number 3 is /WP (Write Protection pin) ( will tell you about it in the below section) and IO2  in case of Dual/Quad SPI.Pin number 4 is GND (Ground).Pin number 5 is DI(Data Input), that is MOSI pin in case of standard SPI and IO0 in case of DUAL/QUAD SPI.Pin number 6 is CLK, the Clock pin of SPI communication.Pin number 7 is /HOLD or /RESET  pin ( will tell you about it in the below section) and IO3 in case of Dual/Quad SPI.Pin number 8 is VCC. Let’s just deep dive into the pin description of this IC Chip Select is held high, that is master has not selected the slave and all my pins would be at High impedance. When the CS pin is held low, the master has selected

Table of Contents So guys this is the continued blog on my interfacing W25Q128JV SPI flash memory with STM32 and AVR MCU. So in the last blog we have started with W25Q128 overview, its features and pin descriptions. Now in this blog we are going to talk about following topic: SPI standard instructions. Status and Configuration Registers of W25Q128JV SPI Serial Flash memory. Write protection features. About its block diagram of memory mapping & management.  and then going to understand Status and Configuration Registers. Then in next blog we are going to start with its driver implementation on STM32 and AVR MCU. SPI Standard Instructions So as I have mentioned that module which we are going to use has standard SPI pins only on the breakout module( one can buy this module from robu). Remember the pinout of W25Q128 from last blog??? If not kindly refer to that W25Q128JV SPI Flash Memory: Part1 once before going further in this topic. W25Q128JV IO2 and IO1 pins are not available in the modules which we are going to use and buy. We can operate the SPI at mode 0(0,0) or mode 3(1,1),  that is SPI CPHA or CPOL bits would be either 0,0 or 1,1. W25Q128JV would be used as a slave and host MCU would be used as a master. In standard SPI we can run this IC at frequency of 133MHZ for read-write operations. But in our sample codes i would be using the IC at 1 MHZ. Most Significant bit(MSB) is sent first during the SPI communication. Chip select pin(CS) would be used for selecting the slave. When CS is set as low, the slave is selected and when CS is set as HIGH, the slave would not be selected. Serial Data Input( DI) is the MOSI pin and Serial Data Output(DO) is the MISO pin. Serial Clock Input (CLK) pin is used as Serial Clock for SPI communication. During configuring of SPI pins for our host MCU, CS pin of the host MCU would be configured as Output pin. MOSI pin of the host MCU would be configured as OUTPUT pin. SCLK pin of the host MCU would be configured as INPUT pin. MISO pin of the host MCU would be configured as INPUT pin. Dual and Quad SPI are not of our concern, so we are not going to dig deep into those in this blog. though we are going to discuss standard SPI only if anybody has any things to ask related to Dual and Quad SPI they can reach out to me via gettobyte community. Status and Configuration Registers These are very important registers, plays an important role in configuring and using these memory chips. Their are 3 Status registers, SR1,SR2,SR3. Status register provide the status on the availability of the flash memory array, whether the device is write enabled or disabled, the state of the write protection, QUAD SPI settings, Security register lock status, and Erase/Program suspend status, output driver strength, and power up status. Also, status registers are used to configure the device write protection failures, QUAD SPI settings, Security register OTP locks and output driver strength. Each Status register can be read and write by specific commands. For reading the status register we have to issue the Read status register instructions for reading the corresponding Status register. One can read the Status registers of the memory chip when we want to know the status on the availability of the flash memory array, whether the device is write enabled or disabled, the state of the write protection, QUAD SPI settings, Security register lock status, Erase/Program suspend status, output driver strength, and power up status. For writing the status register we have to issue the write status register instructions for the corresponding Status register. One can write on the status registers when we want to configure the chip for the device write protection failures, QUAD SPI settings, Security register OTP locks and output driver strength. Status Register 1 S0: BUSY bit –> BUSY is a read-only bit in the status register (S0) that is set to a 1 state when the device is executing a Page Program(02h), Quad Page Program(32h), Sector Erase(20h), Block Erase(52h), Chip Erase(60h), Write Status Register(01h,31h,11h) or Erase/Program Security Register instruction(44h/42h). During this time the device will ignore further instructions except for the Read Status Register. So in short we can use this bit inside the while loop or if loop to check whether the device is ready for further instructions or not. erase_sector4KB(read_addr1); // device is executing a erase sector instruction if((ReadSR(ReadSR1) & BUSY_BIT) == 0x01) // Busy bit is set when erase sector instruction is send, so checking that { erase_sector4KB(read_addr1); } S1:WEL –> Write enable latch is also a read-only bit that is set to 1 after executing a Write enable instruction and making the chip in write enabled mode. Prior to every Page Program(02h), Quad Page Program(32h), Sector Erase(20h), Block Erase(52h), Chip Erase(60h), Write Status Register(01h,31h,11h) or Erase/Program Security Register instruction(44h/42h) we have to send the Write enable instruction. So after sending the write enable instruction we can read this bit to check whether Write enable Instruction is executed or not.  It is cleared to 0 when the device is written disabled. Write disabled state occurs after the Page Program(02h), Quad Page Program(32h), Sector Erase(20h), Block Erase(52h), Chip Erase(60h), Write Status Register(01h,31h,11h) or Erase/Program Security Register instruction(44h/42h). So in short we can say that the WEL bit is used to check whether Write enable Instruction is executed or not. S2-S3-S4: Block Protect Bits(BP2, BP1, BP0) –> are read/write bits that can be used to protect the memory array from Program or erase instructions. One can protect ALL, NONE, or PORTION of the memory, corresponding configurations can be done for BP2, BP1, and BP0 bits according to the below tables. Also, see the TB and SEC bits for Write protection configurations S5: Top/Bottom BLOCK Protect(TB)–> This bit controls whether the memory protection has to be performed from TOP