MFRC522 Host Interfaces

MFRC522 can be connected to Host MCU using 3 serial protocols: UART, I2C or SPI.

MFRC522 checks the current host interface type.
automatically after performing a power-on or hard reset. The MFRC522 IC identifies the host
interface by sensing the logic levels on the below pins after the reset phase. 

The MFRC522 is equipped with a series of registers that allow the Host MCU to access its functional description blocks. To ensure the proper functioning of the MFRC522, the Host MCU must initialize and configure these functional blocks by sending the corresponding register addresses.

Each register is essentially an address byte that is transmitted from the Host MCU. Depending on the function described in the register section, read/write operations are performed on the corresponding address byte.

It is crucial to properly initialize and configure these functional blocks to ensure the optimal performance of the MFRC522. By understanding the purpose of each register and its corresponding function, the Host MCU can effectively communicate with the MFRC522 and achieve the desired results.

–> MFRC522_write_register()

–> MFRC522_Read_register()

MFRC522 Interrupts

MFRC522 can trigger the interrupts, when certain events occur. There are 8 events as shown in below table when interrupt can be triggered.

When above event occurs, IRQ pin is used to interrupt the host. IRQ pin signal is asserted and host MCU can use its interrupt handling capabilities (basically NVIC if we are talking about ARM based MCU) on what to do when corresponding interrupt has occurred.

• Status1Reg Register IRq bit is used to indicate if any interrupt source has been triggerered.

• Which interrupt has been triggered is indicated by ComIrqReg and DivIrqReg Register. 

• Which interrupts to be configured and behavior of IRQ pin is configured by ComIEReg and DivIEReg Register.

MFRC522 Time Unit

There is a Timer unit in MFRC522, that is used for multiple purposes. Timer unit is essential for maintaing the configuring the clock and analog interfaces. Also timer unit can be used for following features:

1. Timeout counter
2. Watchdog counter
3. Stopwatch
4. Programmable one shot
5. Periodical trigger

Timer has an input clock of 13.56 MHz derived from the 27.12 MHz quartz crystal oscillator. The timer consists of 2 stages: prescaler and counter.

• The prescaler(TPrescaler) is a 12-bit counter. That can be configured using TModeReg register’s TPrescaler_Hi[3:0] and TPrescalerReg register’s TPrescaler[7:0] bits.
• The Reload value for the counter is defined by 16 bits between 0 & 65535 in the TReloadReg register.
• The current value of the timer is indicated in the TCounterVAlReg Register. 

MFRC522 FIFO

FIFO overview

The MFRC522 contains an internal FIFO buffer of 64 bytes, which is equivalent to 8 x 64 bits. This buffer is utilized for both input and output data streams. The host MCU has the capability to perform both Read and Write operations on this FIFO. The host MCU sends commands to PCD for communication with PICC. these commands are specified in ISO14443 A standard,  which is then inputted into the FIFO. When the PICC responds to these commands, the response is also stored in the FIFO. The host MCU can then read the FIFO to obtain the response from the PICC.

The FIFO buffer is a crucial component in the communication process between the host MCU and the PICC. It allows for efficient data transfer and ensures that all responses are stored in a centralized location. The ability to perform both Read and Write operations on the FIFO provides flexibility and control to the host MCU. By utilizing the FIFO buffer, the communication process is streamlined and optimized for maximum efficiency.

About FIFO registers

FIFO buffer input and output data bus is connected to the FIFODataReg register.  Writing to this register stores one byte in the FIFO buffer and increments the internal FIFO buffer write pointer. Reading from this register shows the FIFO buffer contents stored in FIFO read pointer and decrements the FIFO buffer read pointer.

Only one FIFO buffer has been implemented which can be used for input and output. The microcontroller must
ensure that there is not any unintentional FIFO buffer accesses.

The FIFOLevelReg is utilized to determine the number of bytes stored in the FIFO. This register is particularly useful in checking the number of bytes received in the FIFO buffer when the PICC sends a response to the PCD command. By using the FIFOLevelReg, you can easily keep track of the amount of data stored in the FIFO, which is essential in ensuring the smooth operation of your system.

One can also get the status of FIFO buffer using status and error registers.

• FIFO buffer almost full warning can be got to know from Status1Reg register’s HiAlert bit.
• FIFO buffer almost empty warning can be got to know from Status1Reg register’s LoAlert bit.
• FIFO buffer overflow warning, using ErrorReg register’s BufferOvfl bit.

MFRC522 CRC

MFRC522 has a Cyclic Rebudency Check (CRC) coprocessor to check the integrity of the data when data from PICC is received or when data is wriiten to PICC.

• CRC has preset value 0000h, 6363h, A671h or FFFFh. We can configure the preset values using ModeReg CRCPreset[1:0].
• CRC polynomial for the 16-bit CRC is fixed to x^16 + x^12 + x^5 + 1.
• CRCResultReg register indicates the result of the CRC calculation.
• CRC algorithm which is used is according to ISO/IEC 14443 A and ITU-T.

To perform the CRC calculation refer its state machine in below section.

MFRC522 Command Set

MFRC522 operation is determined by certain commands. According to these commands, correspondingly MFRC522 would be performing some action.

So, it’s like at first, we will configure the FIFO, CRC, Interrupts and timer unit. After that Host MCU will instruct the commands to MFRC522 in order to tell what it has to do. Host MCU will write the command code to the CommandReg Register. 

Main commands that would be used are Idle, Transceive, CalcCRC and Transmit commands. Transceive command is the one which has to be sent from Host MCU to MFRC522 to send the FIFO buffer data to the antenna, which is further propagated to the RFID readers. And according to the data which we have written in FIFO RFID readers would act and give response.

Each command that needs a data bit stream (or data byte stream) as an input immediately processes any data in the FIFO buffer. An exception to this rule is the
Transceive command. Using this command, transmission is started with the BitFramingReg register’s StartSend bit.