Overview So, in this blog we will be covering another alternate functionality of GPIO pins i.e SPI (Serial Peripheral Interface). Previously we hve covered following peripherals implementation in STM32F103 MCU’s. ADC(Analog To Digital Converter) in STM32F103 UART Peripheral in STM32F103 GPIO Peripheral in S32K144 MCU Clock Peripheral in STM32F103 PWM on STM32F103 SPI is a synchronous and full duplex communication between a master and several slave devices. It is used in devices or sensors in which speed is a priority . It operates at data transmission rate 8 Mbits or more. The protocol uses 3 or usually 4 wires for data transmission and receiver .It is used by various sensors and modules such as OLED Display, BMP280 , RC522 , DAC , Shift Registers etc. SPI Theory The SPI uses 2 pins for data transfer SDIN and SDO , SCLK clock for synchronization of data transfer between 2 chips, CE chip select that is used to initiate and terminate the data transfer. SDI  =  MOSI SDO  =  MISO SCLK  =  SCK CE  =  SS MOSI: MASTER OUT SLAVE IN This pin is used to send data from master to slave MISO: MASTER IN SLAVE OUT Lorem ipsum dolor sit amet, consectetur adipisi cing elit, sed do eiusmod tempor incididunt ut abore et dolore magna SCK: SERIAL CLOCK This is used to generate clock to synchronize data transfer between the master and slave device . This is generated by master SS:SLAVE SELECT Used to select the particular slave to send data . Besides SPI communication the SPI interface can switch between I2S communication protocol that is a synchronous serial communication interface. It supports 4 audio standards including the I2S Philips standard, the MSB- and LSB-justified standards, and the PCM standard. The operating modes can be full duplex(4 wires) and half duplex (6 wires) Multi Mode Configuration Multiple subnodes can be used with a single SPI main. The subnodes can be connected in regular mode or daisy-chain mode.   How Data is Transmitted in SPI Initially SCK is enabled that starts the transmission The master sets the SS line low of the slave Data is usually shifted out with most significant bit  first , shifting a new least significant bit into the same register Data in slave side is shifted into least significant bit of the register Hence after all the shifting is done the master and slave has transferred the data If more data is to be exchanged the registers are reloaded and the process is repeated When no more data transmission is there the master stops toggling the SCK and deselects the slave using SS   SPI Peripheral Bus Modes Before discussing about the various bus modes we will be discussing the clock phase and polarity i.e CPOL:Clock Polarity and CPHA:Clock Phase and it is the combination of CPOL and CPHA that is referred to as Bus Modes. CPOL = 0  Active state of clock = 1 Idle state of clock= 0 Means the sampling on the first edge      CPHA = 0 – Data is captured on the rising edge and output on falling edge      CPHA = 1 – Data is captured on the falling edge and output on the rising edge        CPOL = 1 Active state of clock = 0 Idle state of clock = 1 Means sampling is on the second edge          CPHA = 0 – Data is captured on the falling edge and output on rising edge        CPHA = 1 – Data is captured on the rising edge and output on the falling edge SPI Features in STM32F103 Full-duplex synchronous transfers on three lines   Simplex synchronous transfers on two lines with or without a bidirectional data line 8- or 16-bit transfer frame format selection  Multimaster mode capability   8 master mode baud rate prescalers (fPCLK/2 max.)  Slave mode frequency (fPCLK/2 max)   Faster communication for both master and slave   NSS management by hardware or software for both master and slave: dynamic change of master/slave operations   Programmable clock polarity and phase Programmable data order with MSB-first or LSB-first shifting  Dedicated transmission and reception flags with interrupt capability   SPI bus busy status flag   Hardware CRC feature for reliable communication:   – CRC value can be transmitted as last byte in Tx mode  – Automatic CRC error checking for last received byte  Master mode fault, overrun and CRC error flags with interrupt capability   1-byte transmission and reception buffer with DMA capability: Tx and Rx requests SPI Instances in STM32F103 SPI instances vary from microcontroller to microcontroller from 1 in stmf103c6t6a to 6 in stm32f7 each having different pins NSS pulse mode , TI mode and hardware crc calculations SPI1 features PA5 as SCK , PA6 as MOSI  and PA7 as MISO SPI2 features PB3 as SCK, PB4 as MISO and PB5 as MOSI.  NSS Management in SPI protocol for STM32F103 NSS line can to be driven via 2 modes Software Mode- SS is driven internally by firmware Hardware Mode – A dedicated GPIO pin is used to drive the SS line Also NSS features NSS output and output disabled mode. Output mode is used only when device operates in master mode and it is disabled allowing mutli master capability NSS hardware mode must be used in TI mode . CPHA and CPOL are forced to conform to Texas Instrument (TI) protocol requirements. In this NSS signal pulses at the end of every transmitted byte APPLICATIONS OF SPI PROTOCOL Application 1 Memory Devices- SD-Card, MMC, EEPROM and FLASH Application 2 Sensors- Temperature and pressure (BMP280) Application 3 Control Devices -ADC, DAC, Audio Codec Application 4 Others- Camera Lens , RTC, LCD , Touch Screen RFID Module interfacing with STM32F103 W25Q SPI Flash Memory ST77389 LCD Display with STM32F103 NRF24L01 RF Module with STM32F103 How to Configure SPI Peripheral for STM32F103 We would be using STM32 HAL and STM32CubeIDE for using the SPI peripheral in STM32F103 in this blog tutorial series. SPI BLOCK DIAGRAM SPI CONFIGURATION ALERNATE FUNCTION MAPPING CONFIGURATION IN STM32CUBEIDE FIG 1- Selecting MOSI, MISO , SS and SCK pins