Decoding the working of MFRC522 RFID Receivers to interface them with Host MCU/MPU
In the last blog I talked about the basics of MPU6050, this time let’s see how to interface it with the STM32 based controller and get the values of accelerometer and Gyro sensor. But before starting first, let’s see the I2C block and the STM32 I2C block to get some idea of the basic structure of the I2C protocol. Figure 1: I2C Hardware Circuit The above circuit diagram shows the hardware connection of the I2C protocol in open drain configuration. The external pull up resistors are being used to make the circuit work efficiently. These days the controllers come with the internal pull up resistors so while writing the code for the same these resistors can be pulled up in the configuration. Before proceeding further lets understand certain terms like pull up, pull down, open drain etc. While using an I/O pin, in the digital domain it has values as LOGIC 1 (HIGH), LOGIC 0 (LOW) and Z-STATE (HIGH IMPEDANCE or FLOATING or TRI-STATE). The purpose of pull up and pull down is to maintain these states of the pin while working. PULL-UP means that the pin is internally connected to the power supply via a resistor and is read as LOGIC 1. PULL-DOWN means that the pin is internally connected to the ground via a resistor and is read as LOGIC 0. In between the two in the configuration, when the pin is neither pull-up nor pull-down and the analog value cannot be represented in the logic value, this state is termed as Z-STATE where there is a floating value. Figure 2: Pull-up and Pull-Down Configuration Now let’s understand the Push-Pull and Open Drain configurations. PUSH-PULL Configuration: This configuration consist of a pair of complementary transistors which works as: For LOGIC 0, the transistor connected to the ground is turned on to sink an electric current from the external circuit. For LOGIC 1, the transistor connected to the power supply is turned on, and it provides an electric current to the external circuit connected to the output pin. The slave address of the MPU-6050 id 0b110100x, a 7-bit long. Here the LSB bit i.e.x in the 7-bit long address is determined by the logic level at AD0 pin.If x=0 i.e., pin AD0 is Logic LOW otherwise Logic HIGH. Figure 3: Push-Pull Configuration Figure 4: The Logic 0 and 1 for Push-Pull Configuration OPEN-DRAIN Configuration: This configuration consist of a single transistors which works as: For LOGIC 0, the transistor connected to the ground is turned on to sink an electric current from the external circuit. For LOGIC 1, it cannot supply any electric current to the external load because the output pin is floating, connected to neither the power supply nor the ground. Hence the Open-Drain has two states LOGIC 0 (LOW) and LOGIC 1 (Z-STATE). This configuration use external pull up resistor. Figure 5: Open-Drain Configuration Figure 6: The Logic 0 and 1 for Open-Drain Configuration I2C Let’s analyze the functional block diagram of the STM32. As shown in the figure, the I2C protocol consists of SDA and SCL lines along with an additional pin SMBA used in SMB protocol known as System Management Bus. The figure shows that there is a single Data Register along with the single Shift Register as the protocol is half -duplex. The address block is also there and a comparator to compare the addresses. The control logic consists of Control Register (CR 1 and CR2) and Status Registers (SR1 and SR2) along with the Clock Control Register for generating the clock for the communication. Figure 7: I2C Block Diagram I2C Implementation Of Figure 9: Pin Connections Above is the pin connection of the MPU6050 with the STM32F411CE. Now set up the stm32 environment as follows: Step 1 Step 2 Step 1 Set up the RCC ad the SYS in the STM32Cube IDE as shown: Step 2 Now enable the I2C1 in the standard mode. Now starting with the code create a mpu6050.h file in the Inc folder and mpu6050.c file in Scr folder. We are all done. Let’s start with the code. In total there are around 80 registers in the IC but during the code all the registers are not required there are certain sets of registers which we are going to use which we will be defining in the header file mpu6050.h. These registers are: Name of the Register Address of the Register (Hex) Function REG_MPU6050_ADDR 0xD0 It is the device address for the MPU6050 module REG_SMPLRT_DIV 0x19 This register specifies the divider from the gyroscope output rate used to generate the Sample Rate for the MPU-6050. REG_GYRO_CONFIG 0x1B This register is used to trigger gyroscope self-test and configure the gyroscopes’ full scale range. REG_ACCEL_CONFIG 0x1C This register is used to trigger the accelerometer self test and configure the accelerometer full scale range. This register also configures the Digital High Pass Filter (DHPF). REG_ACCEL_XOUT_H 0x3B These registers store the most recent accelerometer measurements. REG_TEMP_OUT_H 0x41 These registers store the most recent temperature sensor measurement. REG_GYRO_XOUT_H 0x43 These registers store the most recent gyroscope measurements. REG_PWR_MGMT_1 0x6B This register allows the user to configure the power mode and clock source. It also provides a bit for resetting the entire device, and a bit for disabling the temperature sensor. REG_WHO_AM_I 0x75 This register is used to verify the identity of the device. The contents of WHO_AM_I are the upper 6 bits of the MPU-60X0’s 7-bit I2C address. The least significant bit of the MPU-60X0’s I2C address is determined by the value of the AD0 pin. The value of the AD0 pin is not reflected in this register. Apart from these registers we have two structures and the function definitions that we are using in the main file. Lets now jump directly towards the mpu6050.c file and see how things are working. In this phase, keep in mind the 3 things. Initializing the mpu6050. Read the RAW values of accelerometer and gyroscope Convert the RAR values to ‘g’ and ‘dps’ for Accelerometer
Table of Contents So continuing with the blog series of, W25Q128 SPI based flash memory\’s , in the previous blogs W25Q128JV SPI Flash Memory: Part1 | gettobyte W25Q128JV SPI Flash Memory: Part2 | gettobyte we have gone through the introduction and overview for W25Q128JV flash memory\’s. From this blog we are going to start with the Application and Device driver development of W25Q128JV IC. The Driver which i am going to develop in this blog will be generic can be used with any MCU, by just replacing the SPI API\’s. This application driver will be generic and simple one which will be having API\’s to perform basic Operation on this chip. We will be creating the 2 files, header file and source file(.h &.c) for W25Q128JV Application driver. Header file(.h) will be having all the Macros, Typedefs, Enums, Structures and function declarations. Source file(.c) will be having all the function definitions and local variables to be used in the driver. Header file (W25Q128JV.h) First thing that we are going to do is define the Object like Macro\’s for all the registers of W25Q128JV in the header file(.h) of W25Q128JV. Macros are widely used in Embedded Programming for referring the registers address with the acronym of the Register names, so that it is easy for developer/user to understand the code or using the API. Like, above if we want to read the JEDECID of the chip, instead of writing 0x9F in the Application code we can pass the Macro JEDECID. (Though we are not going to use all the registers of W25Q128, as in this blog we are just going to make the driver for following features. The Application driver will be having API\’s for reading-writing the data, erasing the data, reading-writing of Status registers, reading JEDEC ID , chip erase and chip initialise.) /* * w25q128jv.h * * Created on: 15-Apr-2021 * Author: kunal */ #define WriteEnable 0x06 #define WriteDisable 0x04 #define Dummybyte 0xA5 #define ReadSR1 0x05 #define WriteSR1 0x01 #define ReadSR2 0x35 //0x35: 00110101 #define WriteSR2 0x31 #define ReadSR3 0x15 #define WriteSR3 0x11 #define Write_Enab_for_Vol_status_regist 0x50 #define ReadData 0x03 #define WriteData 0x02 #define ReadDataFast 0x0B #define JEDECID 0x9F #define UinqueID 0x4B #define SectErase4KB 0x20 #define SectErase32KB 0x52 #define SectErase64KB 0xD8 #define chiperase 0xC7 #define reset1 0x66 #define reset2 0x99 #define read_addr1 0x020000 #define read_addr2 0x030000 #define read_addr3 0x040000 #define BUSY_BIT 0x01 #define WRITE_ENABLE_LATCH 0x02 Next thing in Header file will be the function definitions that would be used for interacting with the W25Q128JV flash memory\’s. void W25_Reset (void); void WriteEnable_flash(); void W25_Read_Data(uint32_t addr, char block[], uint32_t sz); void W25_Write_Data(uint32_t addr, char block[], uint32_t sz); uint32_t W25_Read_ID(void); void W25_Ini(void); void erase_sector4KB(uint32_t addr); void erase_sector32KB(uint32_t addr); void erase_sector64KB(uint32_t addr); void chip_erase(); void Uinque_ID(uint8_t uinque[]); void WriteSR(uint8_t SR_address, uint8_t SR_data); uint8_t ReadSR(uint8_t SR_address); void WaitForWriteEnd(void); Apart from Object like Macro\’s and Function definition\’s their would be 2 additional function like Macro\’s. //For STM32 CUBEMX #define cs_set() HAL_GPIO_WritePin(GPIOA,GPIO_PIN_4,GPIO_PIN_SET) #define cs_reset() HAL_GPIO_WritePin(GPIOA,GPIO_PIN_4,GPIO_PIN_RESET) //For STM32 BareMetal #define cs_set() GPIOA->ODR |= GPIO_ODR_ODR4; #define cs_reset() GPIOA->ODR &= ~GPIO_ODR_ODR4; As we are going to interface the W25Q128JV via SPI peripheral to our MCU\’s, in which MCU would be the Master device and W25Q128JV would be slave device. And in SPI -> Chip Select/Chip Enable pin is used for selecting the slave. Thus these 2 Macro\’s would be used for selecting the slave before the SPI instructions are send ( by using the cs_set()) and then deselecting the slave after the SPI instructions( by using the cs_reset()). Source file(W25q128JV.c) This file would be having all the function declarations of the functions which are defined in (W25Q128JV.h). The 2 most important API\’s which will Send and Receive the SPI commands are: void SPI1_Send (uint8_t *dt, uint16_t cnt) { HAL_SPI_Transmit (&hspi1, dt, cnt, 5000); } void SPI1_Recv (uint8_t *dt, uint16_t cnt) { HAL_SPI_Receive (&hspi1, dt, cnt, 5000); } API\’s Explained for Device Driver of W25Q128JV: void SPI1_Send () This function is wrapper for transmitting the data via SPI. not be used directly in Application driver, but it will always be called by Other API\’s of the driver to send the command to W25Q via SPI. It has 2 parameters: 1) uint8_t *dt –>pointer to store the data that will be transmitted from the Host MCU to W25Q128JV. 2) uint16_t cnt –> Variable that will be storing the size of data that has to be transmitted from MCU to W25Q128JV. void SPI1_Send (uint8_t *dt, uint16_t cnt) { HAL_SPI_Transmit (&hspi1, dt, cnt, 5000); } void SPI1_Recv() This function is wrapper for receiving the data via SPI. This API is also not used directly by the Application Driver, but will be used by the other API\’s of the driver for receivng the data from W25Q via SPI. It also has 2 parameters: uint8_t *dt –> pointer to store the data that will be received from the W25Q128JV. uint16_t cnt –> variable that will be storing the size of data that has to be received. void SPI1_Recv (uint8_t *dt, uint16_t cnt) { HAL_SPI_Receive (&hspi1, dt, cnt, 5000); } void W25_Reset(): W25Q SPI flash Ic\’s come in small package and they have limited number of the pins. Thus W25Q provides the software reset instruction feature. User/Developer can reset the W25Q by sending the specified instructions to W25Q via SPI. After reset the device will come to its default state and loose all volatile content. Enable reset – 0x66( reset 1 macro) and Reset – 0x99( reset 2 macro)are the instructions that has to be send for generating the software reset. These 2 instructions has to be send in sequence, as any other command after the Enable reset command( 0x66) apart from Reset(0x99) will disable the reset procedure. Once the reset command is accepted it woulfd take approx 30us to reset the W25Q IC. void W25_Reset (void) { cs_reset(); tx_buf[0] = reset1; tx_buf[1] = reset2; SPI1_Send(tx_buf, 2); cs_set(); } void WriteEnable_flash(): In W25Q, before writing to any Page, Erasing any sector/block or performing full chip erase. We have to send the Write enable Instruction via SPI.
Table of Contents So guys this is the continued blog on my interfacing W25Q128JV SPI flash memory with STM32 and AVR MCU. So in the last blog we have started with W25Q128 overview, its features and pin descriptions. Now in this blog we are going to talk about following topic: SPI standard instructions. Status and Configuration Registers of W25Q128JV SPI Serial Flash memory. Write protection features. About its block diagram of memory mapping & management. and then going to understand Status and Configuration Registers. Then in next blog we are going to start with its driver implementation on STM32 and AVR MCU. SPI Standard Instructions So as I have mentioned that module which we are going to use has standard SPI pins only on the breakout module( one can buy this module from robu). Remember the pinout of W25Q128 from last blog??? If not kindly refer to that W25Q128JV SPI Flash Memory: Part1 once before going further in this topic. W25Q128JV IO2 and IO1 pins are not available in the modules which we are going to use and buy. We can operate the SPI at mode 0(0,0) or mode 3(1,1), that is SPI CPHA or CPOL bits would be either 0,0 or 1,1. W25Q128JV would be used as a slave and host MCU would be used as a master. In standard SPI we can run this IC at frequency of 133MHZ for read-write operations. But in our sample codes i would be using the IC at 1 MHZ. Most Significant bit(MSB) is sent first during the SPI communication. Chip select pin(CS) would be used for selecting the slave. When CS is set as low, the slave is selected and when CS is set as HIGH, the slave would not be selected. Serial Data Input( DI) is the MOSI pin and Serial Data Output(DO) is the MISO pin. Serial Clock Input (CLK) pin is used as Serial Clock for SPI communication. During configuring of SPI pins for our host MCU, CS pin of the host MCU would be configured as Output pin. MOSI pin of the host MCU would be configured as OUTPUT pin. SCLK pin of the host MCU would be configured as INPUT pin. MISO pin of the host MCU would be configured as INPUT pin. Dual and Quad SPI are not of our concern, so we are not going to dig deep into those in this blog. though we are going to discuss standard SPI only if anybody has any things to ask related to Dual and Quad SPI they can reach out to me via gettobyte community. Status and Configuration Registers These are very important registers, plays an important role in configuring and using these memory chips. Their are 3 Status registers, SR1,SR2,SR3. Status register provide the status on the availability of the flash memory array, whether the device is write enabled or disabled, the state of the write protection, QUAD SPI settings, Security register lock status, and Erase/Program suspend status, output driver strength, and power up status. Also, status registers are used to configure the device write protection failures, QUAD SPI settings, Security register OTP locks and output driver strength. Each Status register can be read and write by specific commands. For reading the status register we have to issue the Read status register instructions for reading the corresponding Status register. One can read the Status registers of the memory chip when we want to know the status on the availability of the flash memory array, whether the device is write enabled or disabled, the state of the write protection, QUAD SPI settings, Security register lock status, Erase/Program suspend status, output driver strength, and power up status. For writing the status register we have to issue the write status register instructions for the corresponding Status register. One can write on the status registers when we want to configure the chip for the device write protection failures, QUAD SPI settings, Security register OTP locks and output driver strength. Status Register 1 S0: BUSY bit –> BUSY is a read-only bit in the status register (S0) that is set to a 1 state when the device is executing a Page Program(02h), Quad Page Program(32h), Sector Erase(20h), Block Erase(52h), Chip Erase(60h), Write Status Register(01h,31h,11h) or Erase/Program Security Register instruction(44h/42h). During this time the device will ignore further instructions except for the Read Status Register. So in short we can use this bit inside the while loop or if loop to check whether the device is ready for further instructions or not. erase_sector4KB(read_addr1); // device is executing a erase sector instruction if((ReadSR(ReadSR1) & BUSY_BIT) == 0x01) // Busy bit is set when erase sector instruction is send, so checking that { erase_sector4KB(read_addr1); } S1:WEL –> Write enable latch is also a read-only bit that is set to 1 after executing a Write enable instruction and making the chip in write enabled mode. Prior to every Page Program(02h), Quad Page Program(32h), Sector Erase(20h), Block Erase(52h), Chip Erase(60h), Write Status Register(01h,31h,11h) or Erase/Program Security Register instruction(44h/42h) we have to send the Write enable instruction. So after sending the write enable instruction we can read this bit to check whether Write enable Instruction is executed or not. It is cleared to 0 when the device is written disabled. Write disabled state occurs after the Page Program(02h), Quad Page Program(32h), Sector Erase(20h), Block Erase(52h), Chip Erase(60h), Write Status Register(01h,31h,11h) or Erase/Program Security Register instruction(44h/42h). So in short we can say that the WEL bit is used to check whether Write enable Instruction is executed or not. S2-S3-S4: Block Protect Bits(BP2, BP1, BP0) –> are read/write bits that can be used to protect the memory array from Program or erase instructions. One can protect ALL, NONE, or PORTION of the memory, corresponding configurations can be done for BP2, BP1, and BP0 bits according to the below tables. Also, see the TB and SEC bits for Write protection configurations S5: Top/Bottom BLOCK Protect(TB)–> This bit controls whether the memory protection has to be performed from TOP
Table of Contents W25Q128JV SPI Flash Memory interfacing with STM32 and AVR MCU So hello guys, welcome back to the Gettobyte once again. As I have told you that we are going to start with application codes also, so now in this blog what we are going to do?? We are going to interface the W25Q128JV SPI Serial flash memory module to our STM32 MCU and AVR8 MCU. Now let’s look at how this module looks. This module is very small and packed into small sizes. One can buy it easily from the Amazon Website. This module has 6 pins: VCC, GND, and 4 SPI Communication pins( MOSI, MISO, CE & SCK). But the IC has much more pins, that I will be briefing below. W25Q128JV SPI Flash Memory module Now starting with this Flash memory, In this blog, I will be telling you about its: General description of the IC. Features of this Serial Flash Memory. Pin Description. In the next subsequent blogs will be making the application code on AVR and STM32 MCU using SPI peripheral and peripheral driver. At first, will be making the application code on AVR MCU and then on STM32 MCU. So now moving forward, let’s begin our journey to it. General Description of W25Q SPI flash memory So starting with W25Q128JV. These are the Serial communication-based Flash memories into which we can store data. These can work as RAM memory for memory constraint embedded MCUs. We can transfer data from these memory chips in standard SPI serial communication up to a frequency of 133 MHZ and when used in Dual/Quad SPI Serial communication, data transfer frequency can go up to 236MHZ/532 MHZ. So one can read, write and fetch data from these memory chips at very high frequencies. These have 65536 programmable page lengths and in total there are 256 pages. That means it has 256 pages and on each page, we can write 65536 bytes. W25Q SPI flash memory depicted as a book On each byte of these pages, we can read and write at a redundancy of 10000 times. Up to 256 bytes can be programmed at a time. We will go into more detail when we will understand its block diagram of memory mapping and management. Features of W25Q SPI Flash Memory It can run on Standard SPI, DUAL SPI, and QUAD SPI. Standard SPI: is traditional SPI Protocol which has CLK,CS,MISO(DO),MOSI(DI) pins. In this, we have 1 pin(MOSI) for sending data from Master to Slave and another pin (MISO) for sending data from slave to master. It can run at Max speed of 133MHZ for standard SPI. To know more about SPI, refer to this blog Dual SPI: In DUAL SPI, we have 2 Output/Input pins. Which means at a time we can send data from 2 pins and receive data from 2 pins. Refer the below image, DI becomes IO0 and D0 becomes IO1, so at a time we can send and receive data from both of those pins. As 1 byte has 8 bits and bits 0 and 1 of my one byte are being transmitted or received simultaneously, thus our data transfer becomes 2x then standard SPI, where only 1 bit is commuted at a time. In Dual SPI Max speed it can run at is 266 MHZ. DUAL SPI QUAD SPI: In QUAD SPI, we have 4 Output/Input pins. Which means at a time we can send data from 4 pins and receive data from 4 pins. IO0,IO1,IO2,IO3 are the 4 pins from which data is commuted between slave and master. In Quad SPI MAX speed it can run at is 532 MHZ. QUAD SPI One can perform 100k program-erase cycles per sector and it has data retention for more than 20 years. Efficient continuously read for about 8/16/32 byte warp. Byte warp here means that it can read memory continuously in the chunks of 8/16/32 bytes in one single time. Lets say it is reading in 8 byte wrap, so at first read it will read 0-7 bytes, then in next 8-15 bytes, then 16-23 bytes. Then the other important thing is Advance Security features which this IC has. You will be able to understand these features in better way when we will go through the Status and Configuration registers of this IC. On the memory chip, We can lock the certain memory bytes, that is no one can write or read on configured memory bytes or size. We can use the OTP (one time password) to have password based memory protection We can access the memory bytes of the IC, in Blocks(64 KB), sectors(4KB) or single byte. Starting from the Top of memory or from the Bottom of memory. PINOUT of the W25Q128 Flash memory chip So W25Q128 has 8 pins. Depending on the package we have, the number of pins of the IC can increase or decrease. The module which we will be using is packaging WSON.Pin number 1 is CE (Chip Select), used to select the SPI slave by making a LOW signal to this pinPin number 2 is DO (Data Output), that is MISO pin in case of standard SPI and IO1 in case of DUAL/QUAD SPI.Pin number 3 is /WP (Write Protection pin) ( will tell you about it in the below section) and IO2 in case of Dual/Quad SPI.Pin number 4 is GND (Ground).Pin number 5 is DI(Data Input), that is MOSI pin in case of standard SPI and IO0 in case of DUAL/QUAD SPI.Pin number 6 is CLK, the Clock pin of SPI communication.Pin number 7 is /HOLD or /RESET pin ( will tell you about it in the below section) and IO3 in case of Dual/Quad SPI.Pin number 8 is VCC. Let’s just deep dive into the pin description of this IC Chip Select is held high, that is master has not selected the slave and all my pins would be at High impedance. When the CS pin is held low, the master has selected