ADC Peripheral in S32K144
Number of ADCs and Channels
–> S32K144 contains two 12-bit SAR ADC modules, ADC0 and ADC1. Each ADC supports up to 16 external analog input channels. Note that ADCx_SEy refer to Channel y of ADCx.
DMA support for ADC
ADC Interleaved Channel Functionality
–> ADC interleaving allows multiple ADCs to sample the same signal alternately, improving performance by increasing sampling speed without overloading a single ADC. On devices with two ADCs, specific channels support this feature. For example, ADC0_SE4 and ADC1_SE14 can either work independently or interleave to sample a signal from PTB0. This interleaving is enabled by the SIM_CHIPCTL[ADC_INTERLEAVE_EN] bit, and other channels like ADC0_SE5/ADC1_SE15 can interleave on different pins (PTB1, PTB13, PTB14).
Internal Supply Monitoring
–> ADC peripheral can also be used to monitor the internal supply. This monitoring is done through ADC0 internal channel 0.
Referencing Option for ADC
–> The ADC offers two reference voltage options:
- VREFH/VREFL: The primary reference option.
- VALTH/VREFL: An alternate reference option.
–> You can select between these references using the ADCx_SC2[REFSEL] bit. In S32K1xx devices, VALTH is equivalent to VDDA. If a package doesn’t have dedicated VREFH/VREFL pins, VREFH is internally tied to VDDA and VREFL to VSSA. When an external VREFH is available, it should either match VDDA or be within an allowed range below it. VREFH must not exceed VDDA, and VREFL should always connect to VSSA.
–> In a nutshell, you can change the reference voltage for ADC conversion as per user requirements.
Trigger Sources Available for ADC
-> In ADC systems, triggers are signals that start the conversion process, while pre-triggers are used to select or control specific ADC channels before conversion begins. They allow flexible control over when and how ADC conversions are initiated.
-> ADC triggers and pre-triggers control when conversions start and which ADC channels are used. The Programmable Delay Block (PDB) or Trigger Multiplexer (TRGMUX) provides flexible trigger options:
PDB Triggering: Automatically triggers ADC conversions and controls channels via up to 8 pre-triggers, reducing CPU involvement. Each PDB pairs with an ADC (PDB0-ADC0, PDB1-ADC1).
TRGMUX Triggering: Offers flexible ADC triggers using external/internal signals. Modules like CMP, LPIT, RTC, and LPTMR can trigger the ADC. TRGMUX enables different peripherals to start ADC conversions without the PDB.
-> The trigger source is controlled by SIM_ADCOPT[ADCxTRGSEL], allowing the selection of PDB or TRGMUX based on application needs.
-> Hardware Triggering Schemes:
Default Scheme (PDB): The most common method is using the PDB to trigger the ADC. This approach is suggested for general use because of its simplicity and automatic trigger mechanism.
Alternative Scheme (TRGMUX): TRGMUX provides another option for hardware triggering, offering more flexibility in selecting which peripherals or pins will initiate ADC conversions.
-> The SIM_ADCOPT[ADCxTRGSEL] field is used to control and configure the source of ADC triggers, allowing the system to choose between PDB or TRGMUX based on the application needs.
To completely understand this Block Diagram, follow our course on AUTOSAR ADC.
Trigger Selection for ADC
–> You can select any combination of trigger enable and trigger for the ADC, but once selected, they cannot be changed on-the-fly. There are specific steps for switching the trigger or pre-trigger sources:
–> To Change the Trigger Source:
- Stop the current trigger generation.
- Wait for 2.5 cycles of the ADC operating clock and 1.5 cycles of the ADC host interface clock, allowing the last trigger to latch.
- Check the
ADC_SC2[TRGSTLAT]status until it becomes 0, indicating all queued conversions are completed. - Update the trigger source as needed.
- Restart the trigger generation unit.
–> For Immediate Trigger Change:
- Stop the current trigger generation.
- Flush the queued triggers by setting
ADC_CFG1[CLRLTRG], except the one currently in progress. - Wait for 2.5 cycles of the ADC operating clock.
- Check
ADC_SC2[TRGSTLAT]until it becomes 0. - Update the trigger source.
- Restart the trigger generation unit.
–> Note: If these steps aren’t followed, some triggers might be missed without being reported.
Trigger Handling and Capturing
–> The four lower triggers can be latched, meaning trigger requests from any selected source are captured and processed one at a time. The ADC handles each latched trigger request sequentially, starting the next only after the current one is complete. This ensures that only one request is processed at a time while others wait in the queue.
–> If a trigger request is repeated for the same trigger (0–3) while it’s being processed or already latched, the new request is ignored, and an error is flagged in the ADC_SC2[TRGSTERR] register.
–> Trigger requests can arrive in two ways: (a) one at a time or (b) simultaneously. However, they are processed in a round-robin order. After completing the Pth request, the system looks for the next available request, starting from P+1 and cycling through until all latched triggers are processed, rolling back to 0 after reaching the last trigger (N-1).
ADC Trigger and Pre-Trigger Configuration
–> The ADC supports two main triggering schemes, as previously explained, through these two paths (using the ADC0_PDB0 triggering example):
- Direct Triggering Path: Used through the PDB starting from channel 4 onward.
- Multiplexed Triggering Path: Utilizes PDB/TRGMUX for channels 0 to 3 via a trigger latching mechanism.
–> When configuring the ADC, you can either:
- Use the direct triggering path with PDB for channels 4 and above, while using PDB for channels 0 to 3, or
- Use only the TRGMUX path for channels 0 to 3.
–> For the PDB direct triggering scheme, ensure that pre-triggers are spaced at least 4 bus clock cycles apart. The table below outlines the ADC triggering configurations and their behavior based on these paths.
–> Note: The PDB only signals a sequence error if two consecutive pre-triggers come from the same PDB channel. If different PDB channels are used, it is important for the software to ensure that there is at least a 4-bus clock cycle delay between the pre-triggers. Otherwise, both conversion results will be invalid.
ADC Low Power Mode and Calibration Scheme
–> The ADC will be available in STOP2 mode.
–>The ADC calibration must be performed using the ADC Status and Control Register 3 (SC3[CAL]) after every reset.
–> Note: To reduce calibration time and overhead, you can run calibration once after each Power-On Reset and store the calibration data in non-volatile memory. This stored data can then be used for calibration after any functional resets, eliminating the need to recalibrate each time.
–> Additionally, after exiting STOP2 power mode, re-calibration is not required because the device maintains continuous power across all modes (STOP2, RUN, and HSRUN), ensuring the ADC meets its specifications as outlined in the datasheet.
Author: Rohan Singhal
