Table of Contents About GPIO Peripheral The pins which can be configured by the software at runtime to perform various functions are called GENERAL-PURPOSE INPUT/OUTPUT (GPIO) pins. With the help of software one can program the GPIO pins mainly as: Digital Output It compares the external voltage signal with a predefined threshold. Digital Input It controls the Voltage of the pin Analog Function It performs ADC (Analog to Digital Conversion) or DAC (Digital to Analog Conversion) Other Functions or Alternate Functions It makes the pin to perform other functions like PWM output, timer-based captures, external interrupts, and various other interfaces like SPI, I2C, UART communications. Before coming to the Schmitt Trigger Understanding, have a quick recap of Pull Up, Pull Down and Open Drain Configurations from MPU6050 Implementation blog Implementation of MPU6050 with STM32 – gettobyte GPIO Input: Schmitt Trigger GPIO Output Speed Slew Rate GPIO Input: Schmitt Trigger A SCHMITT TRIGGER is a device which uses a voltage comparator to convert a noisy or slow signal edge into a clean and desirable edge instantaneously. For a real time system, the external signals do not change instantly, due to slower slew rate which depends on inheritance parasitic capacitance, resistance or an inductor at the input side. As the processor chip has a Schmitt Trigger, it increases the slew rate and increases the noise immunity for the signals which are captured. Let us understand the implementation of the Schmitt Trigger. It consists of a voltage comparator with positive feedback. The output Vout depends between two input voltage V+ and V–. If V+ > V–, Vout is quickly saturated to VSAT, otherwise Vout = 0 For an ideal op-amp, the current flowing through resistor R3 is zero and thus we have Vref = V– The op-amp output Vout has two saturation values, as shown below Vout = VSAT if V– <V+ 0 if V– < V+ However, V+ depends on Vout and Vin· Therefore, Vout depends on both the input Vin and the recent history of Vout· Such an effect is called hysteresis. Using KCL, assuming that the current flow in the non inverting input terminal of op-amp is zero, Vin – V+ /R2 = V+ – Vout / R1 On solving the above equation we will get, Vin = R2Vout + R1Vin / R1 + R2 At the time instant when Vout transits from one saturation value to the other saturation value, we have V+ = Vref Thus, Vref = R2Vout + R1Vin / R1 + R2 Solving further we get, Vin = (1 + R2/ R1)Vref – (R2/R1)Vout As discussed earlier, Vout has only two possible values. If Vout = 0 initially and Vin increases, we can obtain the trigger high threshold VTH at which Vout transits to VSAT: VTH = (1 + R2/R1) Vref – (R2/R1)*0 = (1 + R2/R1)Vref On the other hand, if Vout = VSAT initially and Vin decreases, we can obtain the trigger low threshold VTL at which Vout transits to 0: VTL = (1 + R2/R1) Vref – (R2/R1)VSAT Vout can be determined by comparing it with two thresholds VTH and VTL. When Vin climbs through VTH , Vout is rapidly switched to the upper limit VSAT· Conversely, once Vin falls below VTL, Vout makes a transition to the lower limit. Note that VTH > VTL , i.e., the threshold for switching to high is greater than the threshold of switching to low. A Schmitt trigger when compared, Provide a better boise rejection. Larger threshold for switching high and low for switching. Immune to undesired noise. GPIO Output Speed Slew Rate The SLEW RATE of a GPIO pin is the speed of change of output voltage with respect to unit time. Slew Rate = ΔV/ Δt In simple words, If the GPIO pin changes from LOGIC LEVEL 0 to LOGIC LEVEL 1, the voltage changes from 0V to 5V in just 5µs, then the slew rate is simply 1V/µs. The higher the slew rate, the shorter time the output voltage takes to rise or fall to desired values. Therefore, a higher slew rate allows faster speed at which the processor can toggle the logic level of a GPIO pin. A shorter rise and fall time allows a GPIO pin to change its logic value more rapidly. A high slew rate can result in significant electromagnetic interference (EMI), also known as radio frequency interference (RFI), to nearby electronic circuits. This is due to the large-amplitude and high-frequency harmonics produced by a fast-rising and falling signal, which can cause malfunctions in a victim circuit through radiation, conduction, or induction. To reduce EMI disturbance, a slower slew rate is generally preferred. GPIO IN STM32WB Each GPIO port has 4 32-bit Configuration Registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR) 2 32-bit Data Register (GPIOx_IDR and GPIOx_ODR) A 32-bit Set/Reset Register (GPIOx_BSRR) A 32-bit locking Register (GPIOx_LCKR0 and 2 32-bit Alternate Function Select Register (GPIOX_AFHR and GPIOX_AFLR) Main feature sog GPIO are Output states: push-pull or open drain + pull-up/down Speed selection for each I/O Input states: floating, pull-up/down, analog Fast toggle capable of changing every two clock cycles Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several peripheral functions GPIO Functional Description The port bit of GPIO can be configured by the software depending upon the hardware characteristics in various modes such as: Input floating Input pull-up Input-pull-down Analog Output open-drain with pull-up or pull-down capability Output push-pull with pull-up or pull-down capability Alternate function push-pull with pull-up or pull-down capability Alternate function open-drain with pull-up or pull-down capability Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR register is to allow atomic read/modify access to any of the GPIOx_ODR registers. In this way, there is no risk of an IRQ occurring between the read and the modify access. The above diagram shows the basic structure of a
Table of Contents About STMicroelectronics STMicroelectronics is a leading provider of semiconductor solutions that are seamlessly integrated into billions of electronic devices used by people worldwide on a daily basis. The semiconductor company builds products, solutions, and ecosystems that enable smarter mobility, more efficient power and energy management, and the wide-scale deployment of the Internet of Things and connectivity technologies. To know more about STMicroelectronics refer to its website: www.st.com. Going back in history, ST was formed in 1987 by the merger of two government-owned semiconductor companies: Italian SGS Microelettronica (where SGS stands for Società Generale Semiconduttori, “Semiconductors’ General Company”), and French Thomson Semiconductors, the semiconductor arm of Thomson. In this blog, we are going to start with ST IoT-based Nucleo Board STm32WB55. What is STM32WB Series all about? The STM32WB55xx and STM32WB35xx are advanced multiprotocol wireless devices that boast ultra-low-power consumption. These devices are equipped with a powerful and efficient radio that is compliant with the Bluetooth® Low Energy SIG specification 5 and IEEE 802.15.4-2011 (Zigbee). Additionally, they feature a dedicated Arm® Cortex®-M0+ processor that handles all real-time low-layer operations. These cutting-edge devices are perfect for a wide range of applications that require reliable and efficient wireless communication. Whether you’re working on a smart home project, a wearable device, or an industrial automation system, the STM32WB55xx and STM32WB35xx are the ideal choices. With their advanced features and capabilities, these devices are sure to revolutionize the way we think about wireless communication. So why wait? Start exploring the possibilities today and discover what the STM32WB55xx and STM32WB35xx can do for you! The devices have been meticulously crafted to operate on minimal power and are built around the high-performance Arm® Cortex®-M4 32-bit RISC core, which can operate at a frequency of up to 64 MHz. This core boasts a Floating-point unit (FPU) single precision that supports all Arm® single-precision data-processing instructions and data types. Additionally, it is equipped with a full set of DSP instructions and a memory protection unit (MPU) that enhances application security. These devices have been designed with the utmost care and attention to detail, ensuring that they are not only efficient but also highly effective. The Arm® Cortex®-M4 32-bit RISC core is a powerful tool that enables these devices to perform at an exceptional level, while the FPU single precision and DSP instructions provide unparalleled accuracy and precision. Furthermore, the memory protection unit (MPU) ensures that your applications are secure and protected from any potential threats. Enhanced inter-processor communication is provided by the IPCC with six bidirectional channels. The HSEM provides hardware semaphores used to share common resources between the two processors. The devices embed high-speed memories (up to 1 Mbyte of flash memory for STM32WB55xx, up to 512 Kbytes for STM32WB35xx, up to 256 Kbytes of SRAM for STM32WB55xx, 96 Kbytes for STM32WB35xx), a Quad-SPI flash memory interface (available on all packages) and an extensive range of enhanced I/Os and peripherals.  About STM32WB55 Architecture Memories Security and Safety True random number generator (RNG) RF Subsystem Low Power Modes Clocks and Startup General Purpose Input Output(GPIOs) Direct Memory Access (DMA) Interrupts and Events Analog to Digital Convertor (ADC) Comparators (COMP) Touch Sensing Controller Liquid crystal display controller (LCD) Timers and watchdogs Real-time clock (RTC) and backup registers Inter Integrated Circuit (I2C) Universal Synchronous/Asynchronous Receiver Transmitter (USART) Serial Peripheral Interface(SPI) Serial audio interfaces (SAI) Quad-SPI memory interface (QUADSPI) Architecture Architecture STM32WB55 Architecture The host application is housed on an Arm® Cortex®-M4 CPU (named CPU1) that connects with a generic microcontroller subsystem. The RF subsystem is made up of a specialized Arm® Cortex®-M0+ microprocessor (named CPU2), Bluetooth Low Energy and 802.15.4 digital MAC blocks, an RF analog front end, and proprietary peripherals. All Bluetooth Low Energy and 802.15.4 low-layer stack functions are handled by the RF subsystem, which limits communication with the CPU1 to high-level exchanges. Some functions are shared between the RF subsystem CPU (CPU2) and the Host CPU (CPU1): Flash memories SRAM1, SRAM2a, and SRAM2b (SRAM2a can be retained in Standby mode) Security peripherals (RNG, AES1, PKA) Clock RCC Power control (PWR) Memories Memories STM32WB55 Memories 2.1. Adaptive real-time memory accelerator (ART Accelerator) The ART Accelerator is a memory accelerator optimized for STM32 industry-standard Arm® Cortex®-M4 processors. It balances the inherent performance advantage of the Arm® Cortex®-M4 over flash memory technologies. To release the processor near 80 DMIPS performance at 64 MHz, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 64-bit flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from flash memory at a CPU frequency up to 64 MHz. 2.2. Memory protection unit In order to prevent one task from unintentionally corrupting the memory or resources used by any other active task, the memory protection unit (MPU) is used to manage the CPU1’s accesses to memory. This memory area is organized into up to eight protected areas. The MPU is especially helpful for applications where some critical or certified code must be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). 2.3. Embedded flash memory The STM32WB55xx and STM32WB35xx devices feature, respectively, up to 1 Mbyte and 512 Kbytes of embedded flash memory available for storing programs and data, as well as some customer keys. 2.4. Embedded SRAM The STM32WB55xx devices feature up to 256 Kbytes of embedded SRAM, split in three blocks: SRAM1: up to 192 Kbytes mapped at address 0x2000 0000 SRAM2a: 32 Kbytes located at address 0x2003 0000 also mirrored at 0x1000 0000, with hardware parity check (this SRAM can be retained in Standby mode) SRAM2b: 32 Kbytes located at address 0x2003 8000 (contiguous with SRAM2a) and mirrored at 0x1000 8000 with hardware parity check. Security and Safety Security and Safety The STM32WB55xx contain many security blocks both for the Bluetooth Low Energy or IEEE 802.15.4 and the Host application. It includes: Customer storage of the Bluetooth Low Energy and