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S32K144 Peripherals

CAN Peripheral in Automotive Controller(NXP S32K144: ElecronicsV3 Development Board)

Motive To know about CAN peripheral in S32K144 Microcontroller, in terms of functional description and block diagram. To understand how FlexCAN peripheral  works in NXP S32K144 MCU’s.( concept of message buffer, mailbox, fifo, meesage id table )(Done) To know how to use CAN peripheral by state machine diagrams. Picking different feature points and explaining their state machines.( Not Right now) To mention FlexCAN features and specs and giving just small brief. To use CAN protocol in NXP Semiconductors S32K1xx Microcontroller’s, there is a peripheral present in S32K1xx series of MCU: The Flex CAN Module. The FlexCAN module fully implements the CAN protocol specification, including the CAN with Flexible Data rate (CAN FD) protocol and the CAN 2.0 version B protocol. It supports both standard and extended message frames, as well as long payloads upto 64 bytes in the case of CAN FD. FlexCAN Module is a peripheral in NXP S32K series of Microcontrollers. All NXP S32K1 and S32K3 microcontrollers have same module FlexCAN which is to be used for doing CAN communication via these microcontrollers. FlexCAN is IP of NXP Semiconductors, that is used in their Automotive Microcontrollers as a microcontroller peripheral which is used for CAN communication. NXP S32K1xx and S32K3xx series of microcontrollers are used in making car ECU’s. In car ECU’s we often have to do the CAN communication for data transfer between 2 ECU nodes. In those cases FlexCAN module is used to do communication via CAN protocol. To know about how CAN communication is done via microcontrollers will recommend reading previous blog: CAN protocol in embedded. What is FlexCAN Module FlexCAN Module is a Microcontroller peripheral in NXP Semiconductors S32 series of microcontroller for doing CAN communication via CAN protocol. S32 series have number of microcontrollers, for understanding we are going to refer S32K144 microcontroller, as this blog series is specific to S32K144 MCU. There can be multiple instances of FlexCAN module in a microcontroller. Like in S32K144 MCU it has 3 instances of FlexCAN module, whereas in S32K344 has 5 instances of FlexCAN module. By instance we mean, number of counts. So, in S32K144 we have 3 FlexCAN modules, meaning 3 communication channels of CAN be done via S32K144. In S32K344 we have 5 FlexCAN modules, meaning 5 communication channels can be done via S32K344. Previous slide Next slide Now for doing CAN communication, FlexCAN module would be using CAN pins of the microcontroller to physically transmit and receive CAN data. The CAN pins are termed as CAN_Rx-CAN_Tx pins in the case of S32K144 MCU and FlexCAN_Tx-FlexCAN_Rx in the case of S32K344 MCU. CAN_Rx & FlexCAN_Rx for receiving pins and CAN_Tx & FlexCAN_Tx for transmitting pins. Each FlexCAN instance in a microcontroller might have different features. Like in S32K144, FlexCAN module 0 has 32 Message buffers, while FlexCAN module 1 and 2 have 32 message buffers. Each Instance of FlexCAN has their own FlexCAN peripheral registers. Which starts at mentioned address of microcontroller memory.  These address are named as FlexCAN instance base address. Now which pin to use via which instance is logically mapped as per numbering. FlexCAN0 would be using CAN0_Tx and CAN0_Rx pins. FlexCAN1 would be using CAN1_Tx and CAN1_Rx pins and so on. Now further for each CAN instance there are number of pins available. Meaning let’s say we want to use FlexCAN module0 of S32K144 MCU. For that we will be using CAN0_Tx and CAN0_Rx pins. CAN0_Tx and CAN0_Rx pins can be mapped to number of pins of microcontroller. As shown in Figure We have to set the alternate function registers of the microcontroller to configure the pin that we want to use for corresponding Instance. This pin configuration part is handled by Port Peripheral of the S32K144 Microcontroller. For setting the speed of communication of FlexCAN module, we have to configure its clock and baurate settings. The Clock to FlexCAN module is fed from Clock peripheral of MCU and then FlexCAN module baudrate can be set by application as per their requirements. Block Diagram of FlexCAN Module FlexCAN peripheral block diagram understanding Working of FlexCAN Module FlexCAN module implements the CAN protocol according to the ISO 11898-1 standard and CAN2.0B protocol specifications. CAN 2.0B protocol specification defines the properties and features in CAN protocol (Standard CAN and Extended CAN) and ISO-11898-1 standard specifies how outgoing and incoming CAN data should be managed so that CAN properties are achieved. In FlexCAN module, message buffer space is being termed as Embedded RAM. Both Terms would be used interchangeably throughout the blog. FlexCAN peripheral has a fixed Embedded RAM Space which is used to process the CAN data. In S32K1xx Microcontroller’s, the Embedded RAM is of 512 bytes.( Explain for chapter of can peripheral register where address range of message buffer is specified) Each FlexCAN instance in S32K144 MCU has their own Message buffer, but they are of different sizes.( explain from instance feature difference table and then comparing that to above point statement) FlexCAN instance 0 has 512 bytes and FlexCAN instance 1&2 has 256 bytes of Embedded RAM. The Embedded RAM in FlexCAN Peripheral space starts from address of 0x0080 offset of corresponding FlexCAN instance base address. Embedded RAM space is from 0x080-0x280 memory address in case of FlexCAN module 0 and from 0x080-0x180 in case of FlexCAN module 1&2. For FlexCAN Instance 0 message buffer starts at: 0x40024080, FlexCAN instance 1 message buffer starts at 0x40025080 and for FlexCAN instance 2 message buffer starts at 0x4002B080 Now if we zoom in to Embedded RAM space, its is divided by offset of 4 bytes. As Shown in figure. Further, if we zoom in to write/read on Embedded RAM it has a structure, according to which CAN data frame is written/read into it. It is called Message Buffer Structure. We will get into it in message buffer structure section. MailBox Mechanism If we have Standard CAN frame, in which we are sending 8 bytes of payload data, so according to above message structure it is gonna occupy 16 bytes of space.

S32K144 Peripherals

CSEc security sub-system in S32K1 MCU

What is CSEc Peripheral CSEc is a microcontroller peripheral in NXP Semiconductors S32K1 series of Automotive MCU’s. CSEc peripheral is a security subsystem, which is based on SHE standard for doing cryptographic operation and establishing secure communication between the ECUs in the car. Security subsystem is a dedicated subsystem within an IC (Microcontroller or SoC) through which we can perform cryptographic operations in microcontroller and protect cryptographic keys from the software attacks. Broadly there are 2 types of security sub-systems in a microcontroller for doing cryptography operations: Secure Hardware Extension (SHE) Hardware Security Module (HSM) The security-subsystem, which we are discussing in this blog: CSEc Module, is based on SHE standard security sub-system. That means using the CSEc peripheral present in S32K144 MCU, we can perform symmetric crypto operations and secure up to 17 user keys. To know more about the SHE standard, refer to this blog. Configuration of CSEc peripheral As CSEc peripheral is SHE standard based security-subsystem and in SHE standard all the controlling of the crypto algorithms and operation’s is done via finite state machine or small CPU core. In S32K1 series, it is done via finite state machine thus the control logic for using CSEc peripheral is command wise. There are commands specified for doing crypto operations according to HIS-SHE specification version 1.1 We just need to specify which command to send, and corresponding crypto operations are executed. (make a graphic showing state machine, she specification and commands with elecronicsv2 and s32k144 photo) The state machine algorithm to use CSEc peripheral is implemented in FTFC module of the S32K1 MCU’s. FTFC is a Flash memory module which is a Hardware IP in S32K1 series of MCU which is used to modify flash memory contents. Flash memory configuration, initialization and all other things are done by FTFC module.  Will deep dive into FTFC module in separate blog. For now, to use CSEc peripheral, features have been added to the FTFC module to support SHE functional specification version 1.1. The FTFC module enables encryption, decryption, CMAC generation-verification and algorithms for secure messaging applications. Additional APIs are also available for Secure Boot configuration, True Random Number Generation (TRNG) and Miyaguchi-Prenell compression. The FTFC core takes care of the flash as well as CSEc functionalities. So, to use CSEc peripheral, we need to configure FTFC module. This configuration is flash memory partitioning, we need to partion the flash memory to emulated EEPROM. By doing so, the FTFC module enables encryption, decryption and CMAC generation-verification algorithms for secure messaging applications. The user can configure the FTFC module for emulated-EEPROM operation by issuing a Program Partition Command (PRGPART). The PRGPART command provides flexibility to specify the partition size between emulated-EEPROM operation and normal operations as per user’s wish. To enable CSEc functionality, the device must be configured for emulated-EEPROM operation. The PRGPART command is used to enable CSEc and also provides a mechanism to specify the key size. Depending on the key size, the last 128/256/512 bytes of EEERAM are reduced from the emulated- EEPROM and become un addressable (so as corresponding EEPROM –backup). This storage is secured and utilized to store cryptographic keys. Once the user configures the FTFC module for CSEc functionality and loads the user keys for the security operations, the device is ready for any security related operations as described in the HIS-SHE specifications. //Show practical codes/API and working of flash memeory partionining // understand abput how memory configuration is being done, what size is done and what size is left and which API is used //How to check CSEc peripheral is configured and memory partioning is done. Crypto operation command using CSEc Okay so now once CSEc is being configured and initialized for use now let’s dwell into how to do crypto operations with it. CSEc peripheral uses command-based programming interface. Crypto operations like Encryption, decryption, loading keys, generating keys and etc. all are done via commands. These commands are handled by CSEc PRAM interface. CSEc PRAM interface is a memory area of around 128 bytes. which is divided into 8 sections. Each section is termed as page here. Starting from page 0 to page 7. Each page of 16 bytes. As shown in below pic. So, we send the command by writing it on page 0 according to the command header specified below and with the command some additional information required by that command and in return we get the result on pages 1-7. The Structure of the command header is standard for all the commands, command header is divided into 6 bytes. –> FuncID: Function Identification (ID) field is a 1 bit long and specifies the security command to be executed. Valid from 0x00 to 0x16. In the code enum One can relate CSEc PRAM interface as a Sheet. That sheet is divided into 8 horizontal lines are. Terminologies to refer to these lines is pages. So their are total 8 pages, starting from page 0 to page 7. Now in first page 0, we write the command In the above image, first page Page 0, includes the command header (Page 0, Word 0) and message control length (Page 0, Word 3). The rest of the pages are utilized for input/output data information. Writing to the command header triggers the macro to lock the CSEc PRAM interface and start the CSEc operation. Hence, to setup a CSEc command, the user should first enter data information followed by message length information and must write command header last. Cryptographic Keys in CSEc Lorem ipsum dolor sit amet, consectetur adipiscing elit. Ut elit tellus, luctus nec ullamcorper mattis, pulvinar dapibus leo. Cryptographic ciphers in CSEc Lorem ipsum dolor sit amet, consectetur adipiscing elit. Ut elit tellus, luctus nec ullamcorper mattis, pulvinar dapibus leo. Cryptographic Operations in CSEc Lorem ipsum dolor sit amet, consectetur adipiscing elit. Ut elit tellus, luctus nec ullamcorper mattis, pulvinar dapibus leo. Features of CSEc Peripheral Lorem ipsum dolor sit amet, consectetur adipiscing elit. Ut elit tellus, luctus nec ullamcorper mattis, pulvinar dapibus leo. CSEc Peripheral has following

S32K144 Peripherals

Clock Peripheral in S32K144 MCU

Table of Contents Objective So hello guys, welcome back to NXP Semiconductors S32K144 MCU Tutorial series. In the last blog we just started with S32K144 MCU. In this blog we are going to explore the clock peripheral of this MCU. Going to Start with Clock peripheral. Objective would be to get familiarity with clock peripheral for S32K144 MCU. How to do clock configuration in S32K144 MCU using S32 Design Studio Config tools. Going to understand the how to use GPIO peripheral via S32K SDK/pins driver. Would also be demonstrating the blink LED sketch for GPIO in the end. https://youtu.be/4egrZ6kwVys Clock Peripheral in S32K144 The clock peripherals of S32k1xx have 3 modules that configure the clocks of the S32K1xx MCU’s. The clock peripherals are basically divided into three modules  System clock generator Low power oscillator Peripheral clock control System clock generator: – This Module generates the Core system clock which is the most important and crucial part. Via this Core system clock, all the peripherals get the clock frequency. So, for generating core system clocks there are 4 sources that can be done. The SCG supports four clock sources, as below: System Oscillator(SOSC):– the system oscillator in conjunction with an external crystal or resonator. That generates a reference clock for the MCU. The frequency of SOSC lies in between XTAL & EXTAL… Fast internal reference clock (FIRC_CLK):- an internally generated 48MHZ clock, which can be used as a clock source for other on-chip peripherals. Slow internal reference clock (SIRC_CLK):– an internally generated 8MHZ clock, which can be used as a clock source for other on-chip peripherals. System phase-locked loop (SPLL):– phase-locked loop that has a VCO(voltage-controlled oscillator) that generates an output signal whose frequency can be adjusted by an input voltage. Peripheral clock control (PCC):- This module basically configures, controls, and generates the clock for all the peripherals of the MCU via system clock frequency. To conserve the power most modules’ clocks can be turned off by configuring the CGC field of the peripheral control register in the PCC module. These fields are cleared after any reset, which disables the peripheral clock of the corresponding module. Note: We will be mainly focusing on the above two clock modules only for our initial development. Understanding and learning. Low power oscillator (LPO):- an internally generated low power oscillator clock with a typical frequency of 128 kHz which can be used as the clock source for modules operational in low power modes. How to configure clock peripheral in S32K144 using S32 Design Studio IDE Trending Today Getting Started with S32 Design Studio Part 3 Getting Started with S32 Design Studio Part 2 What is OLED Technology? CONFIGURING THE OLED WITH STM32 MCU Clock peripheral of S32K144 MCU can be configured using the Clock Configuration tools of S32 Design Studio. These tools provide us with the GUI interface to configure the clock of the MCU. To know in detail about the clock configuration of S32 Design Studio refer to these. Clock diagram View In the clock diagram we can configure the frequency of MCU using the clock tree.This view would be used in this blog for doing system and core clock configuration of MCU. Click HereClock Table ViewIn clock table, view we can see the clock frequency in tabular format of all clock sources and clock outputs of the Microcontrller. This view would be used for seeing summary of system and clock configuration. Click Hereclock peripheralIn clock peripheral we can see all the clock frequency that is set by us to configure output clock. This view would not be used in the systema nd clock configuration, this view is mainly for peripheral clock configuration. Click HereClock Consumer ViewIn clock consumer we can see all the input & output clock in tabular form.This view would not be used in the systema nd clock configuration, this view is mainly for peripheral clock configuration. Click Here Previous slide Next slide For Demonstration purpose on how to do the Clock Configuration in S32 Design Studio, using the hello world demo example from GPIO Peripheral of S32K144 and configuring its core clock with 16 MHZ external crystal oscillator using SPLL. Step 1 Step 2 Step 3 Step 4 Step 5 Step 6 Step 7 Step 1 Firstly, go to the clock tree view and change the external clock oscillator value (SOSC) from 8mhz to 16mhz. External Crystal Oscillator values SOSC selection in S32 Config tools Step 2 Mow in Clock Tree View. Initially the SPLL, when SOSC is 8mhz as given in the below fig, that is SPLL_VCO is 224 MHz and After dividing by /2, SPLL_CLK becomes 112 MHz Now as we have changed the SOCS value to 16 MHz, so these values have become SPLL_VCO is 448 MHz and after the divider value (/2), SPLL_CLK is 224 Mhz. Now as we can see after 16 MHz, it is showing an error, that is the box has become red, hovering on it we can see what the error is. you need to configure the SPLL_ VCO within 180-320 MHz and SPLL_CLK within 90-160 Mhz. And both of these values are getting out of the limit, because of which the red box comes up. So, calculate the value of dividers and multipliers of SPLL in such a way that it is first of all within the allowed limits, shown in the error box.  Step 3 So, we have selected the Multiplier of SPLL_VCO as 3 and the divider of SPLL_VCO as 36, which results in SPLL_VCO as 192 MHz and after the divider value which is fixed for SPLL that is /2, our SPLL_CLK becomes 96 mhz. Now as SPLL_VCO is 192 MHz and SPLL_CLK is 96 MHz, that is within the allowed limits. So our error box is removed now from SPLL.If the clk is configured properly and you follow the run mode’s clock minimum frequency, then it will not show any error like this.   Step 4 Now we have to select the clock source for the System

S32K144 Peripherals

SPI Peripheral in S32K144 MCU

So hello guys, welcome back to NXP Semiconductors S32K144 MCU Tutorial series. In the last 2 blogs we had started with S32K144 MCU GPIO Peripheral & UART Peripheral . Table of Contents In this blog we are going to explore the SPI Peripheral. Going to Start with SPI peripheral. Objective would be to get. familiarity with SPI peripheral for S32K144 MCU. Would be understanding SPI peripheral from Hardware point of view in S32K144 MCU. Going to understand then how to use SPI peripheral via S32K SDK/lpspi driver. Would also be demonstrating the spi_echo_pall sketch. So read along the blog and do tell me its reviews SPI Peripheral Theory Serial Peripjeral interface is a synchronous serial communication interface used in embedded systems, typically to perform short distance communications between microcontrollers and device. Typical applications include interfacing to LCD displays, memory cards, Secure Digital cards and etc.   SPI Peripheral in S32K144 MCU In S32K144 MCU, SPI protocol can be used via 2 peripherals: LPSPI & FlexIO. LPSPI is referred as Low Power Serial Peripheral Interface. LPSPI is on chip peripheral only to do SPI communication protocol. SPI is a serial protocol which is done via SPI supported peripherals in the Microcontrollers. Also, in S32K144 there is FlexIO peripheral through which on-board serial communication protocols like UART, I2C & SPI can be emulated. So through FlexIO peripheral, also SPI peripheral can be implemented. To know about FlexIO peripheral in S32K144, refer to this blog. Features of SPI via LPSPI peripheral in S32K144 MCU: LPSPI module supports efficient interface to an SPI bus, as a master and slave. LPSPI is designed to use little CPU overhead, with DMA support. LPSPI can generate a DMA request. SPI devices communicate in full duplex mode using a master-slave scheme, with a single master at a time.  Single master can control multiple slave devices using individual slave select (SS) lines. If MCU is configured as Master, then it will generate the frame for reading and wiriting and SPI clock which is synchronous. Supports daisychain for controlling multiple slave sharing the same chip select. Configurable clock polarity and clock phase Master operation supporting upto 4 peripheral chip selects at a time Transmit and receive FIFO of 4 words for both master and slave device. Flexible timing parameters in master mode, including SCK frequency and delays between PCS and SCK edges. Support for Full duplex transfers, supporting 1 bit transfers and receive on each clock edge. Support for full-duplex transfers, supporting 1-bit/2-bit/4-bit transfers and receive on each clock edge. How to get started with I2C peripheral in S32K144 MCU SPI Hardware Pinout in S32K144 MCU LPSPI Pinout and Hardware Instances LPSPI peripheral in S32K144 has 3 instances: LPSPI0, LPSPI1, LPSPI2. In S32K MCU, LPSPI peripheral can be used in serial and parallel data transfers. For this blog we are going to focus on serial data transfers. to know about parallel data transfers, refer to this blog. All the LPSPI instances has following pins, for using them. SCK (Serial clock): This pin is used to generate the clock pulses in SPI communication by the Master. SOUT (Serial data out): This pin is MOSI pin. SIN (Serial Data Input): This pin is MISO pin. PCS [0] (Peripheral Chip Select 0): This pin is used to select the slave in SPI communication. Master device will generate a Low Signal on this Pin to select the Slave. And generate High signal to deselect the Slave. PCS [1]: Peripheral Chip select 1. PCS [2]: Peripheral Chip Select 2. PCS [3]:Peripheral Chip Select 3   Each LPSPI instance in S32K144 supports all the above-mentioned pins, with below mentioned pin details. Refer to this blog to know about pins signal description in S32K144 MCU   LPSPI0 LPSPI1 LPSPI2 LPSPI0 In LPSPI0 there are following number of pins: For PCS0 there are 2 pins For PCS1 there is 1 pin. For PCS2 there is 1 pin. For PCS3 there is 1 pin. For SCK there are 3 pins For SIN there are 3 pins. For SOUT there are 3 pins LPSPI0 pins in S32K144 3 pins. LPSPI1 In LPSPI1 there are following number of pins: For PCS0 there are 2 pins For PCS1 there is 1 pin. For PCS2 there is 1 pin. For PCS3 there is 1 pin. For SCK there are 2 pins For SIN there are 2 pins. For SOUT there are 3 pins. LPSPI1 pins in S32K144 LPSPI2 In LPSPI2 there are following number of pins: For PCS0 there are 3 pins For PCS1 there is 1 pin. For PCS2 there is 1 pin. For PCS3 there is 1 pin. For SCK there are 2 pins For SIN there are 2 pins. For SOUT there are 2 pins. LPSPI2 pins in S32K144 MCU How to do LPSPI Pin Configuration In a MCU a single pin can work as multiple function, so we have to configure that which function we need, accordingly pins have to be configured. This configuration of Alternate functions of pins in S32K144 MCU is done by Signal Multiplexing peripheral. One can configure which pin to use for LPI2C, via Signal Multiplexing peripheral, in which there is a register Pin Control Register (PCR) which has Pin Mux Control bits(MUX) for configuring the alternate functions of the pins. For example, we are using LPISPI0. Now in LPISPI0 for using LPSPI0_PCS0, LPSPI0_SCK, LPSPI0_SOUT, LPSPI0_SIN pins one can configure PTB0, PTB2, PTB4, PTE1  pins: You can see SSS column in the excel in that for PTB0 under LPSPI0_PCS has value of 0000_0011. Last 3 bits of this value represents the MUX values to be configured for configuring PTB0 pin as LPSPI0_PCS pin, in PORT_PCRn register. You can see SSS column in the excel in that for PTB2 under LPSPI0_SCK has value of 0000_0011. Last 3 bits of this value represents the MUX values to be configured for configuring PTB2 pin as LPSPI0_SCK pin, in PORT_PCRn register. You can see SSS column in the excel in that for PTB4 under LPSPI0_SOUT has value of 0000_0011. Last 3 bits of this value represents the MUX values to

S32K144 Peripherals

I2C Peripheral in S32K144

So hello guys, welcome back to NXP Semiconductors S32K144 MCU Tutorial series. In the last 2 blogs we had started with S32K144 MCU GPIO Peripheral & UART Peripheral . GPIO Peripheral in S32K144 UART Peripheral in S32K144 MCU In this blog we are going to explore the I2C Peripheral. Going to Start with I2C peripheral. Objective would be to get. familiarity with I2C peripheral for S32K144 MCU. Would be understanding I2C peripheral from Hardware point of view in S32K144 MCU. Going to understand then how to use I2C peripheral via S32K SDK/i2c driver. Would also be demonstrating the i2c_echo_pall sketch. So read along the blog and do tell me its reviews! Table of Contents I2C Peripheral Theory I2C Peripheral is a serial communication protocol which are used to interface external sensor and display screens to the Host MCU. Sensors like IMU sensor, Torque sensor, OLED Display screen and etc To know about I2C peripheral theory, you can refer to this blog. I2C Peripheral in S32K144 MCU In S32K144 MCU, I2C protocol can be used via 2 peripherals: LPI2C & FlexIO. LPI2C is referred as Low Power Inter Integrated Circuit. LPI2C is on chip peripheral only to do I2C communication protocol. I2C is a serial protocol which is done via I2C supported peripherals in the Microocntrollers. Also, in S32K144 there is FlexIO peripheral through which on-board serial communication protocols like UART, I2C & SPI can be emulated. So through FlexIO peripheral, also I2C peripheral can be implemented. To know about FlexIO peripheral in S32K144, refer to this blog. Features of I2C via LPI2C peripheral in S32K144 MCU: LPI2C supports standard-mode, fast -mode , fast-mode plus and ultra -fast modes of operation High Speed Mode(HS) in slave mode. Multi-master support, including synchronization and arbitration. Multi-master means any number of master nodes can be present. Clock stretching support. Slave addressing via 7 bit( upto 2^7 slaves can be connected at same I2C lines) and 10 bit(upto 2^10 slaves can be connected at same I2C lines). Support of DMA and Interrupts for both I2C master & slave. LPI2C also has Support of System Managment Bus Specification, version 2(SMBus), it is used for design of Smart Battery System. Features of LPI2C master: Transmit and Receive FIFO of 4 words. Transmit FIFO can initiate START and STOP conditions for starting I2C communication. As I2C master always initiate the communication session. Flag and interrupts signal to Start Signals, STOP signals, loss of arbitration, unexpected NACK and command word errors. Features of LP12C Slave: There are registers for configuring address if MCU is used as I2C slave. This is done so as to minimize software overhead because of master/slave switching. Software-controllable ACK or NACK. Flag and interrupt signals for end of a packet, STOP condition or bit error detection. How to get started with I2C peripheral in S32K144 MCU I2C Hardware Pinout in S32K144 MCU LPI2C Pinout and Hardware Instances LPI2C peripheral in S32K144 has 1 instance: LPI2I2C0 In S32K MCU, LPI2C peripheral can be used in 4 wire schemes & 2 Wire Scheme. For this blog we are going to focus on 2-wire scheme. To know about 4-wire scheme, refer to this blog. All The LPI2C Instances has 5pins, instead of traditional 2 pins: SCL (Serial Clock): It is used as SCL pin in 2-wire scheme.  SDA (Serial Data):  It is used as SDA pin in 2-wire scheme. HREQ (Host Request): If host request is asserted and the I2C bus is idle, then it will initiate an LPI2C master transfer. SCLS (Secondary I2C clock line): Not used in 2 wire scheme. SDAS (Secondary I2C data line): Not used in 2-wire scheme. Each LPI2C instance in S32K144 supports all the 2 pins, with below mentioned pin details. Refer to this blog to know about Pins Signal description in S32K144 MCU LPI2C0 LPI2C0 In LPI2C0 there are following number of pins: For SDA there are 2 MCU pins. For SCL there are 2 MCU pins. LPI2C0 Pins in S32K144 How to do LPI2C Pin Configuration In a MCU a single pin can work as multiple function, so we have to configure that which function we need, accordingly pins have to be configured. This configuration of Alternate functions of pins in S32K144 MCU is done by Signal Multiplexing peripheral. One can configure which pin to use for LPI2C, via Signal Multiplexing peripheral, in which there is a register Pin Control Register (PCR) which has Pin Mux Control bits(MUX) for configuring the alternate functions of the pins. For example, we are using LPI2C0. Now in LPI2C0 for using SCL-SDA pins one can configure PTA3-PTA2 pins: You can see SSS column in the excel in that for PTA3 under LPI2C0_SCL has value of 0000_0011. Last 3 bits of this value represents the MUX values to be configured for configuring PTA3 pin as LPI2C0_SCL pin, in PORT_PCRn register. You can see SSS column in the excel in that for PTA2 under LPI2C0_SDA has value of 0000_0011. Last 3 bits of this value represents the MUX values to be configured for configuring PTA3 pin as LPI2C0_SDA pin, in PORT_PCRn register. This part of LPUART pins configuration is done internally by S32 SDK/pin driver (Its detail overview is in GPIO Peripheral in S32K144 MCU). When writing the code, we just need to configure the structure  g_pin_InitConfig in which. mux member for the corresponding MCU pin will be assigned value according to last 3 bits of SSS column, as shown below and pass that structure in PINS_DRV_Init(). /*! @brief Definitions/Declarations for BOARD_InitPins Functional Group */ /*! @brief User number of configured pins */ #define NUM_OF_CONFIGURED_PINS0 2 /*! @brief User configuration structure */ pin_settings_config_t g_pin_mux_InitConfigArr0[NUM_OF_CONFIGURED_PINS0] = { { .base = PORTA, .pinPortIdx = 2U, .pullConfig = PORT_INTERNAL_PULL_UP_ENABLED, .driveSelect = PORT_LOW_DRIVE_STRENGTH, .passiveFilter = false, .mux = PORT_MUX_ALT3, .pinLock = false, .intConfig = PORT_DMA_INT_DISABLED, .clearIntFlag = false, .gpioBase = NULL, .digitalFilter = false, }, { .base = PORTA, .pinPortIdx = 3U, .pullConfig = PORT_INTERNAL_PULL_UP_ENABLED, .driveSelect = PORT_LOW_DRIVE_STRENGTH, .passiveFilter = false, .mux = PORT_MUX_ALT3, .pinLock = false, .intConfig = PORT_DMA_INT_DISABLED, .clearIntFlag = false, .gpioBase = NULL, .digitalFilter = false,

S32K144 Peripherals

UART Peripheral in S32K144 MCU

So hello guys, welcome back to NXP Semiconductors S32K144 MCU Tutorial series. In the last blog we had started with S32K144 MCU GPIO Peripheral. In this blog we are going to explore the UART Peripheral. Going to Start with UART peripheral. Objective would be to get. familiarity with UART peripheral for S32K144 MCU. Would be understanding UART peripheral from Hardware point of view in S32K144 MCU. Going to understand then how to use UART peripheral via S32K SDK/uart driver. Would also be demonstrating the uart_echo_pall sketch. So read along the blog and do tell me its reviews! Table of Contents UART Peripheral Theory UART is a serial communication protocol which is used to interface external sensor & IoT modules to the Host MCU. IoT modules like: GSM Module, GPS Module, BLE Modules, WiFi Modules are connected to Host MCU via UART protocol. Thus, understanding of UART communication protocol and its driver implementation, plays a crucial role. To know about UART peripheral in theory, viewers can refer to this blog. LPUART Peripheral in S32K144 MCU In S32K144 MCU, UART can be used via 2 peripherals: LPUART & FlexIO. LPUART is referred as Low Power Universal Asynchronous Receiver/Transmitter. LPUART is onchip peripheral only to do UART communication protocol. UART is a serial communication protocol which is done via UART peripheral in the Microcontrollers. Also, in S32K144, there is FlexIO peripheral through which on-board serial communication protocols like UART, I2C & SPI can be emulated. So, through FlexIO peripheral, also UART peripheral can be implemented. To know about FlexIO peripheral in S32K144, refer to this blog. Features of UART via LPUART peripheral in S32K144 MCU: LPUART peripheral of S32K144 supports full duplex mode and has NRZ data encoding (That is Logic 1 bit represents High value and Logic 0 bit represents Low value). It has programmable Baud rates( LPUART peripheral supports Interrupts mode, DMA mode or pooled operation mode for transmitting/receiving the data using LPUART protocol or for detecting below listed errors while LPUART communication session is happening: Transmit data register empty and transmission complete. Receive data register full. Receive overrun, parity error, framing error, and noise error. Idle receivers detect. Active edge on receive pin. Break detect supporting LIN. Receive data match. S32K144 also supports hardware parity generation and checking to ensure the integrity of the data while LPUART communication is happening. It has Programmable LPUART data length of 7-10 bits and LPUART stop bits of 1-2 bits. S32K144 MCU has feature to use the LPUART peripheral to wake up the MCU (if it is programmed in sleep modes), it can be waked up in either of the 3 below mentioned events: Idle line wakeup Address mark wakeup Receive data match. Support of request to send (RTS) and clear to send (CTS) signals, for hardware flow control,  example of hardware flow control is a half-duplex radio modem to computer interface. Support of IrDA 1.4 format with programmable pulse width for IR communication. LPUART peripheral of S32K144 supports independent FIFO buffer for transmission and receiving of Data. Also, LPUART peripheral FIFO of S32K144 has additional features like: configurable watermark (lowest number of bytes) for transmit and receive buffer, when watermark is achieved corresponding status is changed of LPUART peripheral. Option for receiver to assert request after a configurable number of idle. characters if receive FIFO is not empty. Tx and Rx FIFO in S32K144 for all LPUART Instances both are of 4 words size. 1 Word is 1 byte(8 bits). So FiFo size is 4 byte long(32 bits). LPUART Hardware Pinout in S32K144 MCU LPUART Pinout and Hardware Instances LPUART peripheral in S32K144 has 3 instances: LPUART0, LPUART1, LPUART2. All the LPUART Instances has 4 pins:  RX: Receiving of data TX: Transmission of data CTS: Clear to Send pin for hardware flow control. RTS: Request to Send for hardware flow control. Each LPUART instance supports all the 4 pins, with below mentioned pin details. LPUART0 LPUART1 LPUART2 LPUART0 In LPUART0 there are following number of pins: For RX pin (LPUART Function) there are 3 MCU Pins.  For TX (LPUART Function) there are 3 MCU pins For CTS (LPUART Function) there are 2 MCU pins For RTS (LPUART Function) there are 2 MCU pins. LPUART1 In LPUART1 there are following number of pins: For RX pin (LPUART Function) there are 3 MCU Pins.  For TX (LPUART Function) there are 3 MCU pins For CTS (LPUART Function) there are 3 MCU pins For RTS (LPUART Function) there are 3 MCU pins. LPUART2 In LPUART2 there are following number of pins: For RX pin (LPUART Function) there are 3 MCU Pins.  For TX (LPUART Function) there are 3 MCU pins For CTS (LPUART Function) there are 3 MCU pins For RTS (LPUART Function) there are 3 MCU pins. S32K144 LPUART2 pinout How to use LPUART Pins in S32K144 MCU for doing UART Communication? Now for doing UART communication, we need to connect hardware UART pins of the MCU, for doing so follow the steps: At first select which instance of LPUART wanna use, once selected. As told above their are 3 instances of LPUART in S32K144 MCU. Once selected, then use above excel to short select which pin of corresponding LPUART has to be used.  Lets say we use LPUART1 and use PTC7 and PTC6 as Tx & Rx pins of LPUART. So connect these pins of MCU with external UART Module. Remember Tx pin of MCU is connected to Rx pin of external UART Module and Rx pin of MCU is connected to Tx pin of external UART Module. Here i am going to use USB to serial FTDI connector with Original S32K144 evaluation2 board. With ElecronicsV2 board, it has on-board UART driver IC at LPUART1 PTC7 and PTC6 pins. How to configure UART Peripheral in S32K144 using S32 Design Studio IDE UART Peripheral of S32K144 MCU can be configured using the Peripheral configuration tools of S32 Design Studio. These tools provide us with the GUI interface to configure the UART Peripheral of the MCU. To know in detail

S32K144 Peripherals

GPIO Peripheral in S32K144 MCU

Table of Contents So hello guys, welcome back to NXP Semiconductors S32K144 MCU Tutorial series. In the last blog we just started with S32K144 MCU. In this blog we are going to explore the first peripheral of this MCU. Going to Start with GPIO peripheral. Objective would be to get familiarity with GPIO peripheral for S32K144 MCU. Would be understanding GPIO peripheral from Hardware point of view in S32K144 MCU. Going to understand the how to use GPIO peripheral via S32K SDK/pins driver. Would also be demonstrating the blink LED sketch for GPIO in the end. So read along the blog and do tell me its reviews! GPIO Peripheral Theory General Purpose Input/Output(GPIO) is a crucial peripheral in microcontrollers, enabling interaction with the external world by sending and receiving digital signals. Digital Signals, here are referenced as High and Low Signals. High signal is +5/+3.3V level and Low Signal is 0V level. As MCU’s are digital devices, so it can only understand High and Low Voltage levels. Almost all the pins of the Microcontroller are by default part of the GPIO peripheral, accept from the power pins. Every Pin can be configured in Input or Output State. State of Pins When a pin is configured as Input State, it can detect the level of external signal whether it is high signal or low signal. For example when we press the button, MCU process that as a external signal. Button is connected to one of the GPIO pins of the Microcontroller, which is being configured as Input state and when we press the button a High or Low voltage signal is generated. Which voltage level is generated? is detected by the configured GPIO Pin. When a pin is configured as Output State, it can generate the High Signal or Low Signal to drive the external electronic devices. For example, LEDs are electronic devices which needs High signal to power-on them and low signal to power-off them. So LEDs are connected to one of the GPIO pins of the Microcontroller, which is being configured as Output State and then by programming we can configure the signal that has to be generated from the corresponding configured GPIO pin. Input/output are defacto states of pins, apart from these 2 there are other states too, on which pins can be configured. State of pins can be: Output Input PullUp PullDown Tri-state GPIO pins categorization GPIOs are organized into banks, each requiring a unique identifier to identify a specific pin. These identifiers are commonly referred to as “Ports” and “Pads”. With the vast number of pins available on a microcontroller, it is essential to have a mechanism to reference and utilize them effectively. To simplify this process, GPIO pins are now divided into Ports, with each Port containing a multiple of 8 pins. This division allows for easy referencing and addressing of the pins on the microcontroller. By utilizing this system, developers can efficiently access and manipulate the GPIO pins on a microcontroller, streamlining the development process and improving overall functionality. GPIO In S32K144 MCU In S32K144 MCU, there are 5 ports of GPIO: named as PTA to PTE. Each Port pin has 16 pins. In S32K144 reference manual, GPIO peripheral is being dicided into 2 modules: PORT (Port Control and Interrupt Module) and GPIO (General Purpose Input/Output Module). PORT Module is responsible for Interrupt and Port Control Operations (Like alternate functions, Pull-up/down, drive strength) of the above Ports specified. GPIO module is responsible only for Controlling Input/Output directions of the port pins. Features of GPIO in S32K144 MCU Pins can be configured as Output. Pins can be configured as Input. Pins support the multiplexing of signals, so that a single pin can be do different job(refer to signal multiplexing section). Dedicated Port Output registers for set/clear/toggle the bits. Efficient bit manipulation of the general-purpose outputs is supported through the addition of set, clear, and toggle write-only registers for each port output data register. GPIO module can operate on 3 modes: Run Mode, Stop Mode and Debug Mode GPIO Module is clocked by System clock. GPIO module has a feature of Lock feature, in this feature we can lock the Mode of operation of PIN in one Power Cycle.  Registers of GPIO in S32K144 For simplicity, each GPIO port’s register appear with the same width of 32 bits, corresponding to 32 pins. The actual number of pins per port in S32K144 is 16 pins. So we will be addressing only first 16 bits of the registers, on last remaining 16 bits are irrelevant for us. But in S32K144 there are 16 pins only per port, so we will be accessing only first 16 bits of the registers (0-15), reading & writing on (16-31) will have no effect. In S32K144, there are registers to support 8bit, 16-bit and 32-bit access. Registers of GPIO: GPIO Data Direction register: Direction of GPIO pin GPIO output data register: Output direction of GPIO pin GPIO Input Data Register: Displays the logic value on each pin Efficient bit manipulation of the general-purpose outputs is supported through the addition of set, clear, and toggle write-only registers for each port output data register. Each Port of GPIO has 16 pins. And each pin is referenced as each bit of the above registers. Features of Pin configured as Output: Output: Pin is configured for the GPIO Function and corresponding port data direction register bit is set.  For efficient bit manipulation, there are dedicated output registers for toggling, Set High or Set LOW the pins. Instead of doing the manipulation of pin signals via software using bit manipulation and shifting Features of Pin Configured as Input Input: If Pin is configured for the GPIO function and the corresponding port data direction register bit is clear. GPIO Hardware/Pinout in S32K144 MCU S32K144 MCU comes in 3 pin counts: S32K144_100lqfp, S32K144_64lqfp, S32K144_48lqfp. The one which we will be using is S32K144_100lqfp. S32K144 EVB board which is explained in last blog, has S32K144 MCU of S32K144_100lqfp packaging.  For GPIO

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