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Definition of ARM CoreSight

\”CoreSight is the Debug Architecture from ARM for Debugging and Trace Solutions in Complex SoC designs (Single core and Multi core)\”

CoreSight Provides all the Infrastructure that is required to Debug, Trace, Monitor, and optimize the performance of a Complete System on Chip (SoC)Design.

The Debug and Trace Features of the ARM Cortex M processors (M3/M4/M33/M7/M0, etc.) are designed based on the CoreSight Debug Architecture. This Architecture Covers a Wide Area Including Debug Interface protocols, on chip bus for debug access, Control of debug components, security features, trace data interface and more.

Debug and Trace in Embedded Systems

By now one obvious question to beginners or newbies that must have come in their mind is what is Debug and Trace. What are these features for which we have a whole complete Architecture called CoreSight? Why do we need Debug and Trace solutions in our Processors/Embedded Controllers? Is it not?

For those readers They can check out this blog, providing you clarity and understanding of all such questions.

One can Understand Debug and Trace Feature/Functionality as one of the Block/Unit of the Processor.

Just like We have UART, SPI, I2C, etc. peripherals for our Microcontrollers for which we have separate Block, Architecture, Peripheral Memory Registers for accessing them and Communication Protocol pins in our Microcontroller. Same Way-out Debug/Trace is one of the peripherals which is present in our Processor for which it has its whole architecture and above Marked things.

• ARM Processor has CoreSight Architecture.
• MIPS Processor has EJTAG Architecture.
• IBM PowerPC processor has COP.

(Units/Block of the Processor are not called peripherals, I have used the above term just to make u understand the analogy)

What are Debug Features??

Features are used to observe or modify the state of parts of the design. This is also Called Invasive Debugging

• Execute instructions line by line function i.e., halting the processor after execution of each line of code(single stepping).
• Execute Instructions Function by function i.e., halting the processor after execution of each functions (Step Over)
• Return from the Function (Step Return/Step Out)
• Stop the processor (halting)
• Stop the Processor at a particular à line of code (called Breakpoint) àmemory address (Called Watchpoint) à coded condition of a variable or memory address is achieved (Conditional Breakpoint/Watchpoint)
• On can control the program execution (By points 1-5)so as to examine(Both read or Write) the change in value of bits of the MCU Peripheral registers and Core Processor Registers (like examining the contents of UART peripheral Registers to mark at which line of code data is received or transmitted by seeing the UART Status registers which has corresponding bits to indicate the event of receiving and transmit data).
• Debug frequently involves halting execution once a failure has been observed and collecting state information retrospectively to investigate the problem.

There are 2 Communication Protocols For using Debug Features:

SWD

&

JTAG

JTAG is an industry Standard protocol (IEEE 1149.1) which is used for debugging and boundary scan testing. It is the de facto Serial Protocol which is present in almost every Processor Family other than ARM also like AVR 8 core, MIPS, PowerPC, etc.

To be noted down:

JTAG Requires 4 pins: TCK, TDI, TMS, TDO; the recent signal TRST is optional.

ARM CoreSight Technology introduced the 2 wire Protocol SWD (Serial Wire Debug): SWCK and SWDIO which is used for Debugging all the ARM based Processors.

The Serial Wire debug(SWD) protocol provides the same debug access features and supports parity error detection, which enables better reliability in systems with higher electrical noise. Therefore, the Serial Wire debug protocol is more favorable then JTAG Interface. Also, SWD and JTAG debug protocols share the same Connections: TCK and SWCL use the same pin, TMS and STDIO use the same pin.

 The SWD port alone does not allow real-time tracing.

What are Trace Features??

Trace refers to the process of capturing data that shows information about how the components in a design of a firmware are operating, executing, and performing. This is also Called Non-invasive Debugging.

• It is real-time (with a small timing delay) and can provide a lot of useful information without stopping the processor. Information like:

1. Amount of execution time for each function(Statistical Profiling)
2. Call hierarchy and execution time sequence of functions
3. Event Execution timing(Timestamp)
4. Clock cycles taken for execution of a particular Instruction.

Examine or change the contents of the memory or peripherals at any time, even when the processor is running. This feature is often called on-the-fly memory access.

• Data Trace(Monitoring the Variable or Memory address in Real Time execution of Code  and Plotting their graph).
• Instruction Trace(information about Instruction execution of a Core)ETM & PTM).
• Instrumentation Trace (Printf () Statement via ITM).
• System trace

Trace is an advanced version of Debugging as it analyzes the performance of our firmware code and how efficient it is in terms of memory and efficiency by capturing the various kinds of data when the CPU is running.

For Trace features there are 2 Modes:

1

Serial-Pin model called Serial Wire Viewer à Using Serial Wire Output (SWO) with Serial Wire Debug (SWD) interface.

• The Serial Wire Output (SWO) pin can be used in combination with SWD. It is used by the processor to emit real-time trace data, thus extending the two SWD pins with a third pin. The combination of the two SWD pins and SWO pin enables Serial Wire Viewer (SWV) real-time tracing in compatible Arm® processors.
•  The Serial Wire Viewer (SWV) is a real-time trace technology that uses the Serial Wire Debug (SWD) port and the Serial Wire Output (SWO) pin. The Serial Wire Viewer provides advanced system analysis and real-time tracing without the need to halt the processor to extract the debug information.

2

Multi-pin Trace Port interface (4 data pins + 1 clock pin).

• For Capturing the Data There must be à  Source for generating the Trace data àSinks are the endpoints of trace data à Links provide Connection, triggering and flow of traced data between Source and Sink.
• The Understanding of how these Debug and Trace features are implemented Plays crucial role for the Firmware engineer to work upon Different ARM processors. Correct use of debug and Trace functionalities can highly reduce the development time for Firmware and Performance of our code.

Those who want to dive deep into how these Debug and Trace features are implemented In ARM Processor and want to understand about the CoreSight Architecture and Components can Move onto the next part of Article.

Those who want to Go to the Practical Implementation part of Debug in STM32 MCU using STlinkv2 can follow this link.

Those who want to Go to the Practical Implementation part of Trace in STM32 MCU using STlinkv2(official white one) can follow this link.