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FTM Peripheral in S32K144

FTM Instances and Channels

–> The FlexTimer module (FTM) is a versatile timer with 2 to 8 channels in each of the 4 instances(FTM0, FTM1, FTM2, and FTM3). It supports functions like input capture, output compare, and PWM signal generation for applications such as motor control and power management. It uses a 16-bit counter as its time reference, which can operate in either unsigned or signed mode.

Features of FTM

–> The FlexTimer Module (FTM) offers a range of features to support various timing and control applications, including motor control and power management:

    • Clock Source Options: FTM can use the input clock, fixed frequency clock, or an external clock.
      • The external clock allows synchronization with off-chip sources.
    • Prescaler: Divides the clock by 1, 2, 4, 8, 16, 32, 64, or 128.
    • 16-bit Counter: Can be free-running or set with initial and final values, counting up or up-down.
    • Input Capture Mode: Captures input on rising, falling, or both edges, with optional filters.
    • Output Compare Mode: Allows setting, clearing, or toggling of the output on match.
    • PWM Generation: Supports edge-aligned and center-aligned PWM.
      • Channels can operate in pairs (equal or complementary outputs) or independently.
      • Includes deadtime insertion for complementary pairs.
    • Interrupts: For events like counter overflow, register reload, or fault detection.
    • Fault Handling: Supports up to 4 fault inputs for global control.
    • Quadrature Decoder: For relative position counting and interrupt on position capture.
    • Dithering: Enables finer control of PWM period and duty cycle.

–> Additionally, the FTM is backward compatible with the TPM module and includes write protection for critical registers.

MCU Mode of Operation for FTM

    • In Debug mode, FTM suspends all counting until the chip returns to normal user mode.
    • In Stop mode, all FTM input clocks stop, disabling the FTM until clocks resume.
    • In Wait mode, FTM continues to operate normally.
    • To save power in Wait mode, disable FTM if it’s not needed for real-time reference or interrupt sources.

Functional Explanation of FTM

1. Understanding the Clock Source of FTM 

    • FTM Clock Domain: The FTM operates with a single clock domain—the FTM input clock.
    • CLKS[1:0] Bits: These bits select one of three clock sources for the FTM counter or disable the counter. After reset, CLKS[1:0] = 0:0, meaning no clock source is selected. These bits can be read or written at any time. Disabling the FTM counter (CLKS[1:0] = 0:0) does not affect its value or registers.
    • Fixed Frequency Clock: An alternative clock source that allows the selection of a clock other than the FTM input or external clock. The fixed frequency clock must not exceed half the FTM input clock frequency due to hardware limitations.
    • External Clock: This clock passes through a synchronizer to ensure proper alignment with FTM input clock transitions. The frequency of the external clock must not exceed 1/4 of the FTM input clock frequency to meet Nyquist criteria, accounting for jitter.

2. Clock Prescalar

The selected counter clock source passes through a prescaler, which is a 7-bit counter. The value of the prescaler is set by the PS[2:0] bits. The prescaler determines how the input clock is divided before reaching the FTM counter, allowing for slower counter speeds when necessary.

Concept of Counter in FTM

–> The FlexTimer (FTM) operates using a 16-bit counter that channels use for input or output functions. The FTM counter clock is derived from the selected clock, divided by the prescaler. It supports multiple counting modes:

Modes of Operation:

    1. Up Counting:

      • Selected when:
        • QUADEN = 0
        • CPWMS = 0
      • The starting value is defined by CNTIN, and the final value by MOD. The counter starts at CNTIN, increments to MOD, then reloads with CNTIN and repeats.
      • The period is calculated as:
        Period = (MOD – CNTIN + 1) × (FTM counter clock period).
      • The TOF bit is set when the counter rolls over from MOD to CNTIN.

          2. Up-Down Counting:

      • Selected when:
        • QUADEN = 0
        • CPWMS = 1
      • The counter increments from CNTIN to MOD, then decrements back to CNTIN, and repeats.
      • The period is:
        Period = 2 × (MOD – CNTIN) × (FTM counter clock period).
      • The TOF bit is set when the counter transitions from MOD to MOD-1.

          3. Free Running Counter:

      • Occurs when:
        • FTMEN = 0, and either MOD = 0x0000 or MOD = 0xFFFF.
      • The counter runs from 0x0000 to 0xFFFF continuously. The TOF bit is set when the counter wraps from 0xFFFF to 0x0000.
Counter Reset:

–> The FTM counter can be reset to the value in the CNTIN register by:

    • Writing to the CNT register.
    • Counter synchronization.
    • In Input Capture mode, when ICRST = 1.

–> This setup offers a flexible configuration for timing and PWM generation, making it suitable for various motor and power management applications.

3. Channel Modes

FieldFunctionTypical Use Case
DECAPENEnables dual-edge capture mode.Pulse width or period measurement.
MCOMBINEEnables modified combine mode.Generating more advanced PWM outputs (e.g., complementary PWM).
COMBINECombines two adjacent channels for PWM.Producing complementary PWM for motor control (e.g., H-bridge).
CPWMSSelects between edge-aligned or center-aligned PWM.Reducing harmonics in motor control with center-aligned PWM.

MSA : MSB

 
Select channel mode (e.g., PWM, output compare).Configuring the channel for PWM or Output Compare mode.

ELSA : ELSB

 
Defines output action (set, clear, toggle) on match.Controlling whether a signal is set, cleared, or toggled on match.
     1. Input Capture Mode of FTM

–> The Input Capture mode is selected when:

    • DECAPEN = 0
    • MCOMBINE = 0
    • COMBINE = 0
    • CPWMS = 0
    • MSB = 0:0, and
    • ELSB ≠ 0:0.

–> In input capture mode, the FTM channel captures the current counter value into the CnV register upon a selected edge on the input pin, while the CHF bit is set and an interrupt is generated if CHIE = 1. The input pin acts as an edge-sensitive input, with ELSB determining the triggering edge (rising or falling).

–> Key Features:

    • Writes to the CnV register are ignored while in input capture mode.
    • Input capture functions correctly during Debug mode, capturing the frozen counter value into the CnV register upon an edge event.

–> Filter Functionality:

    • Available only on channels 0, 1, 2, and 3.
    • Maximum detectable frequency is the FTM filter clock divided by 4, in accordance with Nyquist criteria.
    • The counter resets on a state change and continues counting until the signal stabilizes. The value is validated when the counter equals CHnFVAL[3:0].
    • If an opposite edge appears before validation, the counter resets. Pulses shorter than (CHnFVAL[3:0] × 4) consecutive rising edges are deemed glitches and ignored.

–> Counter Reset in Input Capture Mode:

    • If the channel is in input capture mode with ICRST = 1, the counter resets to the CNTIN register value upon detecting an input capture event. This allows the FTM to measure the period or pulse without requiring software subtraction calculations.
    • When the counter resets due to an input capture event, the prescaler counter is also reset.
–> Important Notes:
    • The ICRST bit should only be set when the channel is in input capture mode.
    • Ensure proper configuration of the registers to avoid unpredictable behavior during operation.
     2. Output Compare Mode of FTM

–> Activation Conditions:

    • DECAPEN = 0
    • MCOMBINE = 0
    • COMBINE = 0
    • CPWMS = 0
    • MSB = 0:1

–> Functionality:

    • Generates timed pulses with programmable position, polarity, duration, and frequency.
    • Upon a counter match with the CnV register, the output can be set, cleared, or toggled.
    • In Toggle mode, the output holds its previous state until the first event.

–> Interrupt Behavior:

    • The CHF bit is set, and an interrupt is triggered if CHIE = 1 at the match.

–> ELSB Configuration:

    • If ELSB = 0:0, the CHF bit is set, and the interrupt occurs, but the channel output remains unchanged.
     3. Edge-Aligned PWM Mode of FTM
    • QUADEN = 0
    • DECAPEN = 0
    • MCOMBINE = 0
    • COMBINE = 0
    • CPWMS = 0
    • MSB = 1

–> The PWM period is calculated as (MOD - CNTIN + 1), while the duty cycle (pulse width) is determined by (CnV - CNTIN). In this mode, all PWM signals begin their pulse from the same leading edge, creating a synchronized start across channels.

–> Key behaviors based on ELSB values:

    • 0:0: Sets the CHF bit when the counter reaches CnV, generating an interrupt if enabled, without altering the output.
    • 1:0: Forces the output high on counter overflow (CNTIN reload) and low on counter match (FTM = CnV).
    • X:1: Forces output low on overflow, high on match.

–> Special cases:

    • CnV = 0x0000: Generates a 0% duty cycle, with CHF unset.
    • CnV > MOD: Produces a 100% duty cycle if MOD < 0xFFFF.

–> With CNTIN ≠ 0, the PWM output range adjusts:

    • CnV = CNTIN gives 0% duty.
    • CNTIN < CnV ≤ MOD provides intermediate duty.
    • CNTIN > CnV or CnV > MOD yields a 100% duty cycle.
     4. Center-Aligned PWM Mode of FTM
    • QUADEN = 0
    • DECAPEN = 0
    • MCOMBINE = 0
    • COMBINE = 0
    • CPWMS = 1

–> Pulse Width and Period:

    • Duty cycle = 2 × (CnV - CNTIN), Period = 2 × (MOD - CNTIN)
    • MOD range: 0x0001 to 0x7FFF for clear behavior.

–> Operation:

    • FTM counts up to MOD, then down to CNTIN.
    • CHF bit & interrupt: Triggered at pulse start (down count) and end (up count) when FTM = CnV.

–> Mode Characteristics

    • Aligned pulse centers across channels with CNTIN.
    • CPWM requires all channels in this mode.

–> Channel Actions Based on ELSB

    • 0:0: CHF set at match, output unchanged.
    • 1:0: Output high (down count), low (up count).
    • X:1: Output low (down count), high (up count).

–> Special Duty Cycles

    • CnV = 0 or negative: 0% duty, CHF not set.
    • CnV ≥ MOD: 100% duty, CHF not set.
     5. Combine Mode of FTM
    • QUADEN = 0
    • DECAPEN = 0
    • MCOMBINE = 0
    • COMBINE = 1
    • CPWMS = 0

–> Functionality

    • Combines an even channel (n) with an adjacent odd channel (n+1) to create a PWM signal on the channel (n).

–> PWM Period & Duty Cycle

    • Period: (MOD - CNTIN + 1)
    • Duty Cycle: |C(n+1)V - C(n)V|

–> Interrupts

    • Channel (n) CHF set and interrupt generated if CHIE = 1 at FTM = C(n)V.
    • Channel (n+1) CHF and interrupt if CHIE = 1 at FTM = C(n+1)V.

–> Output Control Based on ELSB Settings

    • ELSB:ELSA = 1:0: Channel (n) output low at CNTIN and C(n+1)V match; high at C(n)V.
    • ELSB:ELSA = X:1: Channel (n) output high at CNTIN and C(n+1)V match; low at C(n)V.

Channel (n+1) Control

    • ELSB:ELSA bits for the channel (n+1) do not impact outputs in Combine mode.
    • If ELSB:ELSA = 0:0 on the channel (n) or (n+1), the respective channel output is not controlled by FTM.
     6. Complementary Mode of FTM
    • QUADEN = 0
    • DECAPEN = 0
    • COMP = 1

Functionality

    • The output of channel (n+1) is the inverse of channel (n)’s output.
    • Note: Not available in Output Compare mode.

–> Other Output Scenarios

    1. Same Output (n+1 and n)

      Selected with:

      • QUADEN = 0, DECAPEN = 0, COMP = 0
      • This applies when channels (n) and (n+1) are in Combine or Modified Combine PWM mode.

           2. Independent Output

                Selected with:

      • QUADEN = 0, DECAPEN = 0, COMP = 0
      • This applies when channel (n) is in Output Compare, EPWM, or CPWM mode.

4. PWM Synchronisation

–> PWM synchronization is a technique that allows real-time adjustments to the generated PWM signal directly from the microcontroller, enabling changes “on the fly.” Through synchronization, key buffered registers—such as MOD, HCR, CNTIN, CnV, OUTMASK, INVCTRL, and SWOCTRL—can be updated with pre-loaded values. These registers store buffered values that are applied during synchronization, allowing smoother PWM transitions. Various update schemes include software or hardware PWM synchronization, or even bypassing buffers altogether, depending on the user requirements of the application.

     A) Hardware Trigger in PWM Synchronisation

–> In PWM synchronization with hardware triggers, the FTM module uses three hardware trigger inputs (TRIG0, TRIG1, and TRIG2), which activate when their respective TRIGn bit is set to 1. Each trigger is synced to the FTM input clock, initiating PWM synchronization on a rising edge at an enabled hardware trigger input. If HWTRIGMODE is set to 0, the TRIGn bit clears either when 0 is written to it or when a trigger event occurs. Notably, if multiple triggers are enabled (e.g., TRIG0 and TRIG1 are set to 1) but only trigger 1 fires, then only TRIG1 clears. If a trigger event and a write operation happen simultaneously, synchronization still starts, but the TRIGn bit stays set due to the write.

–> If HWTRIGMODE is set to 1, the TRIGn bit only clears when 0 is explicitly written to it. This mode is compatible only with enhanced PWM synchronization (when SYNCMODE is set to 1), ensuring that hardware triggers function correctly with synchronized updates in enhanced PWM applications

     B) Software Trigger in PWM Synchronisation

–> A software trigger event occurs when a 1 is written to the SYNC[SWSYNC] bit. The SWSYNC bit then clears either when 0 is written to it or once the PWM synchronization from that software event completes. If another software trigger event is initiated (by writing 1 to SWSYNC) as the prior synchronization is ending, a new PWM synchronization starts, and SWSYNC remains 1.

    • If SYNCMODE = 0, the SWSYNC bit also clears according to the PWMSYNC and REINIT bits. Specifically:

      • If PWMSYNC = 1, or PWMSYNC = 0 and REINIT = 0, the SWSYNC bit clears at the next selected loading point after the software trigger.
      • If PWMSYNC = 0 and REINIT = 1, it clears immediately when the software trigger occurs.

    • If SYNCMODE = 1, SWSYNC clears based on the SWRSTCNT bit:

      • If SWRSTCNT = 0, SWSYNC clears at the next loading point after the software trigger.
      • If SWRSTCNT = 1, SWSYNC clears immediately when the software trigger event happens.

5. Global Time Base (GTB)

–> The Global Time Base (GTB) mechanism on S32K devices enables synchronization across multiple independent FTM modules when more PWM channels are needed than a single FTM can offer. By keeping counters aligned across FTMs, GTB acts as a synchronous signal from a master FTM, ensuring all FTM counters begin counting together under the same clock source and at the same time.

–> GTB configuration uses GTBEEN and GTBEOUT bits in the CONF register:

    • GTBEEN = 1 allows gtb_in to control the FTM counter enable signal.
    • GTBEEN = 0 allows each FTM module to function independently.

–> The gtb_in and gtb_out signals interconnect FTMs, enabling their counters to operate synchronously as a unified time base, giving the appearance of a single module with synchronized PWM channels. However, GTB only synchronizes the start of counting—counters may lose synchronization during extended operation.

Enabling the Global Time Base (GTB)

–> To enable the Global Time Base (GTB) feature for synchronized PWM across multiple FTM modules, follow these steps for each participating module:

    1. Stop the FTM Counter: Set SC[CLKS] to 00b.
    2. Configure the FTM Module: Set up the FTM module with consistent settings across all participating FTMs.
    3. Enable GTB: Set CONF[GTBEEN] to 1 and CONF[GTBEOUT] to 0 simultaneously.
    4. Select a Clock Source: Choose the same clock source for each module by setting SC[CLKS].
    5. Reset the FTM Counter: Write any value to the CNT register.

–> To activate GTB synchronization, set CONF[GTBEOUT] to 1 in the designated master FTM module, which will serve as the time base for other modules.

Rohan Singhal
Author: Rohan Singhal

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Rohan Singhal

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