GPIO Peripheral in S32K144
GPIO Introduction
–> The GPIO module connects to the processor via a high-speed, zero-wait state interface for optimal pin performance. Key features include:
- Flexible Register Access: Supports 8-bit, 16-bit, and 32-bit register operations.
- Direction and Output Control: Data direction and output data registers control each pin when set to GPIO mode, while input data registers show the logic state of each pin in any digital mode if enabled through the Port Control module.
- Efficient Bit Manipulation: Set, clear, and toggle registers enable quick and efficient changes to output states on each port.
Features of GPIO
- Port Data Input Register: Accessible in all digital pin-multiplexing modes, showing the current logic level of each pin.
- Port Data Output Register: Supports set, clear, and toggle operations for efficient pin control.
- Port Data Direction Register: Configures each pin as input or output.
–> Note: The GPIO module operates with the system clock.
MCU Mode of Operation for GPIO
- Run: The GPIO module operates normally.
- Stop: The GPIO module is disabled.
- Debug: The GPIO module operates normally.
GPIO Register Description
- Port Data Output Register (PDOR)
- Port Set Output Register (PSOR)
- Port Clear Output Register (PCOR)
- Port Toggle Output Register (PTOR)
- Port Data Input Register (PDIR)
- Port Data Direction Register (PDDR)
- Port Input Disable Register (PIDR)
–> NOTE: Each of the above-mentioned registers is 32-bit width. As mentioned below, if you change the 18th bit(for example) due to any reason, then your action will only be reflected on the 18th pin.
Port Data Output Register (PDOR)
–> Function: This register sets the logic levels for each general-purpose output pin.
–> NOTE: Avoid modifying pin configuration registers for pins not in your package. Unbonded pins will default to DISABLE for lower power consumption.
- Port Data Output:
- 0b – Logic level 0 is driven on the pin if it’s set for general-purpose output.
- 1b – Logic level 1 is driven on the pin if it’s set for general-purpose output.
- Port Data Output:
Port Set Output Register (PSOR)
–> Function: This register determines whether to set the fields of the PDOR.
- Port Set Output:
Writing to this register affects the corresponding bit in the PDOR:- 0b – No change to PDORn.
- 1b – Sets PDORn to logic 1.
- Port Set Output:
Port Clear Output Register (PCOR)
–> Function: This register clears the fields of the PDOR.
- Port Clear Output:
Writing to this register affects the corresponding bit in PDOR:- 0b – No change to PDORn.
- 1b – Clears PDORn to logic 0.
- Port Clear Output:
Port Toggle Output Register (PTOR)
–> Function: This register toggles the logic levels on each general-purpose output pin.
- Port Toggle Output:
Writing to this register affects the corresponding bit in the PDOR:- 0b – No change to PDORn.
- 1b – Sets PDORn to the opposite of its current state.
- Port Toggle Output:
Port Input Disable Register (PIDR)
–> Function: This register captures the logic levels for each general-purpose input pin.
–> NOTE: Avoid modifying pin configuration registers for pins not in your package. Unbonded pins default to DISABLE for lower power consumption.
- Port Data Input:
- Reads 0 at unimplemented pins. Pins not set for digital functions read 0. If the Port Control and Interrupt module is off, the corresponding bit in PDIR won’t update.
- 0b – Logic level is 0 or not set for digital use.
- 1b – Logic level is 1.
- Port Data Input:
Port Data Direction Register (PDDR)
–> Function: The PDDR configures pins for input or output.
- Port Data Direction:
- 0b – Configures the pin as a general-purpose input (high-Z if the port input is disabled).
- 1b – Configures the pin as a general-purpose output.
- Port Data Direction:
Port Input Disable Register (PIDR)
–> Function: This register disables general-purpose pins from acting as inputs.
- Port Input Disable:
- 0b – Pin is set for General Purpose Input if configured for any digital function.
- 1b – Pin is not set as General Purpose Input; corresponding PDIR bit will read zero.
- Port Input Disable:
Functional Explanation of GPIO
1. General-Purpose Input
–> Each pin’s logic state can be checked using the Port Data Input registers, but there are a few conditions: the right bit in the port input enable register needs to be set, the pin has to be set up for digital use, and the Port Control and Interrupt module has to be active. It’s cool to note that the input pin synchronizers work together with the Port Control and Interrupt module. So, if the module is turned off, the synchronizers will be off too. This setup helps save power when a port isn’t needed for regular input functions!
2. General-Purpose Output
–> You can control the logic state of each pin using the port data output registers and port data direction registers, as long as the pin is set for the GPIO function. Check out these conditions for configuring a pin as input or output:
- IF a pin is configured for the GPIO function and the corresponding port data direction register bit is clear, THEN the pin acts as an input.
- IF a pin is configured for the GPIO function and the corresponding port data direction register bit is set, THEN it acts as an output, and its logic state matches the corresponding port data output register.
–> To make it easier to manage general-purpose outputs, there are pin data sets, pin data clear, and pin data toggle registers. These let you set, clear, or toggle one or more outputs in a single register write! Plus, you don’t need to enable the Port Control and Interrupt module to update the state of the port data direction and output registers, including the set, clear, and toggle registers.
Author: Rohan Singhal
