W25Q128JV SPI Flash Memory: Part2

Table of Contents

So guys this is the continued blog on my interfacing W25Q128JV SPI flash memory with STM32 and AVR MCU. So in the last blog we have started with W25Q128 overview, its features and pin descriptions. Now in this blog we are going to talk about following topic:

• SPI standard instructions.
• Status and Configuration Registers of W25Q128JV SPI Serial Flash memory.
• Write protection features.
• About its block diagram of memory mapping & management.

 and then going to understand Status and Configuration Registers. Then in next blog we are going to start with its driver implementation on STM32 and AVR MCU.

SPI Standard Instructions

So as I have mentioned that module which we are going to use has standard SPI pins only on the breakout module( one can buy this module from robu). Remember the pinout of W25Q128 from last blog??? If not kindly refer to that W25Q128JV SPI Flash Memory: Part1 once before going further in this topic.

W25Q128JV IO2 and IO1 pins are not available in the modules which we are going to use and buy. We can operate the SPI at mode 0(0,0) or mode 3(1,1),  that is SPI CPHA or CPOL bits would be either 0,0 or 1,1. W25Q128JV would be used as a slave and host MCU would be used as a master. In standard SPI we can run this IC at frequency of 133MHZ for read-write operations. But in our sample codes i would be using the IC at 1 MHZ. Most Significant bit(MSB) is sent first during the SPI communication.

Chip select pin(CS) would be used for selecting the slave. When CS is set as low, the slave is selected and when CS is set as HIGH, the slave would not be selected. Serial Data Input( DI) is the MOSI pin and Serial Data Output(DO) is the MISO pin. Serial Clock Input (CLK) pin is used as Serial Clock for SPI communication.

During configuring of SPI pins for our host MCU,

• CS pin of the host MCU would be configured as Output pin.
• MOSI pin of the host MCU would be configured as OUTPUT pin.
• SCLK pin of the host MCU would be configured as INPUT pin.
• MISO pin of the host MCU would be configured as INPUT pin.

Dual and Quad SPI are not of our concern, so we are not going to dig deep into those in this blog. though we are going to discuss standard SPI only if anybody has any things to ask related to Dual and Quad SPI they can reach out to me via gettobyte community.

Status and Configuration Registers

These are very important registers, plays an important role in configuring and using these memory chips. Their are 3 Status registers, SR1,SR2,SR3.

Status register provide the status on the availability of the flash memory array, whether the device is write enabled or disabled, the state of the write protection, QUAD SPI settings, Security register lock status, and Erase/Program suspend status, output driver strength, and power up status. Also, status registers are used to configure the device write protection failures, QUAD SPI settings, Security register OTP locks and output driver strength.

Each Status register can be read and write by specific commands.

For reading the status register we have to issue the Read status register instructions for reading the corresponding Status register. One can read the Status registers of the memory chip when we want to know the status on the availability of the flash memory array, whether the device is write enabled or disabled, the state of the write protection, QUAD SPI settings, Security register lock status, Erase/Program suspend status, output driver strength, and power up status.

For writing the status register we have to issue the write status register instructions for the corresponding Status register. One can write on the status registers when we want to configure the chip for the device write protection failures, QUAD SPI settings, Security register OTP locks and output driver strength.

Status Register 1

• S0: BUSY bit –> BUSY is a read-only bit in the status register (S0) that is set to a 1 state when the device is executing a Page Program(02h), Quad Page Program(32h), Sector Erase(20h), Block Erase(52h), Chip Erase(60h), Write Status Register(01h,31h,11h) or Erase/Program Security Register instruction(44h/42h). During this time the device will ignore further instructions except for the Read Status Register. So in short we can use this bit inside the while loop or if loop to check whether the device is ready for further instructions or not.

erase_sector4KB(read_addr1); // device is executing a erase sector instruction
if((ReadSR(ReadSR1) & BUSY_BIT) == 0x01) // Busy bit is set when erase sector instruction is send, so checking that
{
erase_sector4KB(read_addr1);
}

• S1:WEL –> Write enable latch is also a read-only bit that is set to 1 after executing a Write enable instruction and making the chip in write enabled mode. Prior to every Page Program(02h), Quad Page Program(32h), Sector Erase(20h), Block Erase(52h), Chip Erase(60h), Write Status Register(01h,31h,11h) or Erase/Program Security Register instruction(44h/42h) we have to send the Write enable instruction. So after sending the write enable instruction we can read this bit to check whether Write enable Instruction is executed or not.  It is cleared to 0 when the device is written disabled. Write disabled state occurs after the Page Program(02h), Quad Page Program(32h), Sector Erase(20h), Block Erase(52h), Chip Erase(60h), Write Status Register(01h,31h,11h) or Erase/Program Security Register instruction(44h/42h). So in short we can say that the WEL bit is used to check whether Write enable Instruction is executed or not.

• S2-S3-S4: Block Protect Bits(BP2, BP1, BP0) –> are read/write bits that can be used to protect the memory array from Program or erase instructions. One can protect ALL, NONE, or PORTION of the memory, corresponding configurations can be done for BP2, BP1, and BP0 bits according to the below tables. Also, see the TB and SEC bits for Write protection configurations

• S5: Top/Bottom BLOCK Protect(TB)–> This bit controls whether the memory protection has to be performed from TOP ( TB=0) or Bottom(TB=1) of the memory array. One can see the above table when TB=0, blocks from the end are protected( Protected blocks starting from 255) when TB=1, blocks from starting are protected(Protect blocks Secstarting from 0).
• S6: Sector/Block Protect bit(SEC) –> This bit controls if the Block Protect bits protect the memory array in either 4KB sectors(SEC =1) or 64 KB sectors(SEC=0). One can see the above table under the Protected density column, when SEC = 0 Protected density is in the multiples of 64KB and when SEC = 1 Protected density is in the multiples of 4KB.
• S7: Status Register Protect(SRP) –>

Status Register 2

• S8: Status Register Protect(SRL) –>
• S9: Quad Enable(QE) –> This bit will enable the QUAD SPI operation. When QE = 0, Standard or DUAL SPI operation is used, When QE=1, QUAD SPI is used

// Code HAS TO BE WRITTEN

• S11-S12-S13:
•  
•  
• S14:Complement Protect bit(CMP)–> This bit is also used for Write protection, in conjunction with the above-listed bits. As its name says, complement so when this bit(CMP) is set to 1 array protection set by SEC, TB, BP2, and BP0 will be reversed

Status Register 3

Write Protection

This is a very important thing, though we will not be going to implement any write protection features in our code initially. But I am going to discuss this topic for future projects and drivers, if readers want to skip this part they can.

Write protection is the feature by which we can protect certain memory bytes, sectors, or blocks of the chip from interacting with the outside world.

Now for write protection, there are 2 ways by which we can protect the memory region of SPI flash memory. One thing to tell you is that the WPS bit in Status register 3 decides which  Write protection scheme has to be used. Write protection schemes are:

1. The first one is, that we use the status register protect( SRP, SRL) and block protect bits( CMP, TB, BP[3:0]): this scheme allows us to configure the entire memory array to be read-only.
2. The second one is, that we use the Individual block locks: this scheme allows us to configure the memory blocks( 64 KB) and sectors( 4 KB)  to be read-only. That is all Erase and Write commands will be ignored if the individual block lock bit is set as 1.

So the difference between these 2 schemes is: In individual Block locks we can configure a single individual block of any specific block if we want to protect it. In this, we can protect the particular block 

and in other what we do we protect a certain section of the memory either from the TOP or From Bottom 

Memory block diagram of W25Q128JV

This is next very important thing to understand for using the W25Q SPI flash memory\’s. The flash memory which we are using has 128Mega bits of memory. That is 16MB/16384KB or we can say 16777216 bytes of data can be stored into it. Now further for understanding we will be referring the memory in Kilo bytes and bytes.

The memory of W25Q128 is organized like that of pages of the book. It has 256 pages and in each page we can write 65536 bytes of data. One byte is equivalent to one word. So in short in one page we can write 65536 words. That would be 64KB of data on one single page. Each page in the datasheet of W25Q is referred as blocks. Thus in memory block diagram of W25Q, we can see their are 256 blocks, each of 64KB. First block is referred as BLOCK 0 and last block is referred as BLOCK 255. Also we can calculate the size of page by subtracting the Ending page address with Starting page address. We can address the pages/blocks by their 24 bit address, as shown in below diagram age So at the time of reading and writing the data onto these chips we have to mention the page address.

 

Also one thing which we can mimic from above diagram is that their are 256 lines in every page/block. In each line we can write 256 bytes(Subtract the 0xOOOOFF- 0xOOOOOOO of block 0 would be equal to 256 bytes). So Total number of lines in one page(256)*bytes can be written in one page(256) = Size of one page(65536 bytes).

Further each page is divided into 16 sectors, each sector is of 4KB, that is 4096 bytes. It is like each page is further broken up into 16 sections of 6KB each.

Total size of one page(65536 bytes) * total number of pages(256) would give us total memory of the chip: 16777216 bytes of memory. 

 

That\’s all that has to be understood in Memory representation of W25Q, if you have any further questions/queries mention them in below comments section